SINGLE-PHASE DEVICE-MULTIPLEXING ACTIVE POWER DECOUPLING CASCADED RECTIFIER AND CONTROL METHOD THEREOF

Abstract

A single-phase device-multiplexing active power decoupling cascaded rectifier and control method thereof. The rectifier includes: n device-multiplexing active power decoupling H-bridge units that are cascaded, n≥2; each unit including: a bridge arm H1 and a bridge arm H2 connected in parallel, a decoupling capacitor branch formed by two capacitors connected in series, and a resistive load; a decoupling inductor being connected in series between a midpoint of the decoupling capacitor branch and a midpoint of bridge arm H2; and a bridge arm H1 of a first unit being sequentially connected in series to an inductor, resistor, and power supply, and then connected to a bridge arm H2 of a last unit. A power switch module of an H-bridge rectification unit is multiplexed, which not only realizes unit power factor rectification of the unit, but also provides a loop for secondary ripple power to achieve secondary ripple power decoupling control.

Claims

1. A multi-module single-phase device-multiplexing active power decoupling cascaded rectifier, the rectifier comprising: n device-multiplexing active power decoupling H-bridge units that are cascaded, n≥2; each device-multiplexing active power decoupling H-bridge unit comprising: a bridge arm H1 and a bridge arm H2 connected in parallel, a decoupling capacitor branch formed by two capacitors connected in series, and a resistive load; a decoupling inductor being connected in series between a midpoint of the decoupling capacitor branch and a midpoint of the bridge arm H2; and a midpoint of an bridge arm H1 of a first device-multiplexing active power decoupling H-bridge unit being sequentially connected in series to an inductor Ls, a resistor Rs, and a power supply Us, and then connected to a midpoint of a bridge arm H2 of a last device-multiplexing active power decoupling H-bridge unit.

2. A control method of the multi-module single-phase device-multiplexing active power decoupling cascaded rectifier according to claim 1, comprising: adding up instantaneous voltages outputted by a controller as a total system voltage through direct current (DC)-side voltage closed-loop control; generating, according to a deviation between an instantaneous voltage P.sub.Vi of each cascaded H-bridge unit and a virtual average voltage, a DC bus voltage deviation modulation signal factor of each cascaded H-bridge unit; generating a grid-side current reference value according to the total system voltage, calculating a difference between a grid-side inductor current and the grid-side current reference value, and generating a first modulation signal through a proportional resonance (PR) controller; generating a reference value of a decoupling inductor current according to an instantaneous power P.sub.n of each cascaded H-bridge unit, calculating a difference between the decoupling inductor current and the reference value of the decoupling inductor current, and generating a modulated wave signal of a bridge arm H2 of each cascaded H-bridge unit through the PR controller; generating a drive signal of the bridge arm H2 of each cascaded H-bridge unit after comparing the modulated wave signal of the bridge arm H2 of each cascaded H-bridge unit with a carrier signal; superimposing the modulated wave signal of the bridge arm H2 of each cascaded H-bridge unit onto the first modulation signal and then onto a respective DC bus voltage deviation modulation signal factor, to generate a modulated wave signal of a bridge arm H1 of each cascaded H-bridge unit; and generating a drive signal of the bridge arm H1 of each cascaded H-bridge unit based on the modulated wave signal of the bridge arm H1 of each cascaded H-bridge unit through a carrier phase-shifted modulation technology.

3. A control system of the multi-module single-phase device-multiplexing active power decoupling cascaded rectifier according to claim 1, comprising: a second direct current (DC) bus voltage control module, configured to add up instantaneous voltages outputted by a controller as a total system voltage through DC-side voltage closed-loop control; a voltage balance control module, configured to generate, according to a deviation between an instantaneous voltage P.sub.Vi of each cascaded H-bridge unit and an average voltage, a DC bus voltage deviation modulation signal factor of each cascaded H-bridge unit; a second unit power factor rectification module, configured to generate a grid-side current reference value according to the total system voltage, calculate a difference between a grid-side inductor current and the grid-side current reference value, and generate a first modulation signal through a proportional resonance (PR) controller; a second active power decoupling control module, configured to generate a reference value of a decoupling inductor current according to an instantaneous power P.sub.n of each cascaded H-bridge unit, calculate a difference between the decoupling inductor current and the reference value of the decoupling inductor current, and generate a modulated wave signal of a bridge arm H2 of each cascaded H-bridge unit through the PR controller; a rectification bridge arm modulation signal generation module, configured to superimpose the modulated wave signal of the bridge arm H2 of each cascaded H-bridge unit onto the first modulation signal and then onto a respective DC bus voltage deviation modulation signal factor, to generate a modulated wave signal of a bridge arm H1 of each cascaded H-bridge unit; a rectification bridge arm drive signal generation module, configured to generate a drive signal of the bridge arm H1 of each cascaded H-bridge unit based on the modulated wave signal of the bridge arm H1 of each cascaded H-bridge unit through a carrier phase-shifted modulation technology; and a decoupling bridge arm drive signal generation module, configured to generate a drive signal of the bridge arm H2 of each cascaded H-bridge unit after comparing the modulated wave signal of the bridge arm H2 of each cascaded H-bridge unit with a carrier signal.

4. A terminal device, comprising a processor and a computer-readable storage medium, the processor being configured to implement instructions, the computer-readable storage medium being configured to store a plurality of instructions, the instructions being adapted to be loaded by the processor to perform the control method according to claim 2.

5. A computer-readable storage medium, storing a plurality of instructions, the instructions being adapted to be loaded by a processor of a terminal device to perform the control method according to claim 2.

6. A single-phase device-multiplexing active power decoupling cascaded rectifier, comprising: a bridge arm H1 and a bridge arm H2 connected in parallel, a decoupling capacitor branch formed by two capacitors connected in series, and a resistive load; a decoupling inductor being connected in series between a midpoint of the decoupling capacitor branch and a midpoint of the bridge arm H2; and a midpoint of the bridge arm being sequentially connected in series to an inductor Ls, a resistor Rs, and a power supply Us, and then connected to the midpoint of the bridge arm H2.

7. A control method of the single-phase device-multiplexing active power decoupling cascaded rectifier according to claim 6, comprising: generating a system voltage P in a circuit operation through direct current (DC) bus voltage closed loop control; respectively generating a grid-side current reference value and a reference value of a decoupling inductor current according to the system voltage P; calculating a difference between a grid-side inductor current and the grid-side current reference value, and generating a first modulation wave through a proportional resonance (PR) controller; comparing the decoupling inductor current and the reference value of the decoupling inductor current, and generating a second modulation wave through the PR controller; superimposing the first modulation wave onto the second modulation wave for comparison with a carrier, and generating a first drive signal of a bridge arm H1 switching transistor that is used to drive rectification; and generating a second drive signal of a bridge arm H2 switching transistor that is used to drive decoupling and rectification after comparing the second modulation wave with the carrier.

8. A control system of the single-phase device-multiplexing active power decoupling cascaded rectifier according to claim 6, comprising: a first direct current (DC) bus voltage control module, configured to generate a system voltage P in a circuit operation through DC bus voltage closed loop control; a first unit power factor rectification control module, configured to generate a grid-side current reference value according to the system voltage P, compare a grid-side inductor current with the grid-side current reference value, and generate a first modulation wave through a proportional resonance (PR) controller; a first active power decoupling control module, configured to generate a reference value of a decoupling inductor current according to the system voltage P, compare the decoupling inductor current with the reference value of the decoupling inductor current, and generate a second modulation wave through the PR controller; and a first drive signal generation module, configured to superimpose the first modulation wave onto the second modulation wave for comparison with a carrier, generate a first drive signal of a bridge arm H1 switching transistor that is used to drive rectification, and generate a second drive signal of a bridge arm H2 switching transistor that is used to drive decoupling and rectification after comparing the second modulation wave with the carrier.

9. A terminal device, comprising a processor and a computer-readable storage medium, the processor being configured to implement instructions, the computer-readable storage medium being configured to store a plurality of instructions, the instructions being adapted to be loaded by the processor to perform the control method according to claim 7.

10. A computer-readable storage medium, storing a plurality of instructions, the instructions being adapted to be loaded by a processor of a terminal device to perform the control method according to claim 7.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0045] FIG. 1 is a schematic diagram of a topology of a multi-module single-phase device-multiplexing active power decoupling H-bridge cascaded rectifier in Embodiment 1;

[0046] FIG. 2 is a schematic diagram of a control policy of a multi-module single-phase device-multiplexing active power decoupling H-bridge cascaded rectifier in Embodiment 1;

[0047] FIG. 3(a) is a schematic diagram of a topology of a single-module single-phase device-multiplexing active power decoupling H-bridge rectifier in Embodiment 1;

[0048] FIG. 3(b) is an equivalent circuit of FIG. 3(a);

[0049] FIG. 4 is a schematic diagram of a control policy of active power decoupling in Embodiment 1;

[0050] FIG. 5 is a schematic diagram of a control policy of a single-module single-phase device-multiplexing active power decoupling H-bridge cascaded rectifier in Embodiment 1;

[0051] FIG. 6 is a schematic diagram of a topology of a two-module single-phase device-multiplexing active power decoupling H-bridge cascaded rectifier in Embodiment 2;

[0052] FIG. 7 is a schematic diagram of a control policy of a two-module single-phase device-multiplexing active power decoupling H-bridge cascaded rectifier in Embodiment 2;

[0053] FIG. 8(a) shows waveforms of DC-side output voltages when two modules are cascaded in Embodiment 2;

[0054] FIG. 8(b) shows waveforms of DC-side voltages of two modules in a time period of 0.9-1.0 s in Embodiment 2;

[0055] FIG. 9(a) shows waveforms of a grid-side voltage and current in Embodiment 2;

[0056] FIG. 9(b) shows a waveform of an input-side voltage in Embodiment 2;

[0057] FIG. 10 shows grid-side current and decoupling inductor current waveforms in Embodiment 2;

[0058] FIG. 11 shows waveforms of decoupling capacitor voltages in Embodiment 2;

[0059] FIG. 12 shows waveforms of DC bus voltages in Embodiment 2; and

[0060] FIG. 13(a) to FIG. 13(d) show waveforms of simulated DC output voltages of two modules after adjustment and stabilization at each stage.

DETAILED DESCRIPTION

[0061] It should be noted that the following detailed descriptions are all exemplary and are intended to provide a further understanding of this application. Unless otherwise specified, all technical and scientific terms used in the present invention have the same meaning as commonly understood by a person of ordinary skill in the art to which this application belongs.

[0062] It should be noted that the terms used herein are merely for describing specific implementations, and are not intended to limit exemplary implementations according to this application. As used herein, the singular form is also intended to include the plural form unless the context clearly dictates otherwise. In addition, it should be further understood that, terms “comprise” and/or “include” used in this specification indicate that there are features, steps, operations, devices, components, and/or combinations thereof.

Embodiment 1

[0063] In one or more implementations, a multi-module device-multiplexing active power decoupling single-phase H-bridge cascaded rectifier is disclosed, and a topology thereof is shown in FIG. 1, including: n device-multiplexing active power decoupling H-bridge units (Bridge 1, Bridge 2, . . . , and Bridge n) that are cascaded, DC-side capacitors C.sub.u1, C.sub.l1, . . . , C.sub.u-n, and C.sub.l-n of the units being decoupling capacitors of Bridge 1, . . . , and Bridge n, and u.sub.cu1, u.sub.cl1, . . . , u.sub.cu-n, and u.sub.cl-n being decoupling capacitor voltages; L.sub.r1, . . . , and L.sub.rn being decoupling inductors, i.sub.Lr1, . . . , and i.sub.Lr-n being currents flowing through the decoupling inductors L.sub.r1, . . . , and L.sub.rn; and R.sub.1, . . . , and R.sub.n being DC-side resistive loads, and u.sub.dc1, . . . , and u.sub.dc-n being DC-side output voltages.

[0064] A topology structure of the device-multiplexing active power decoupling H-bridge unit specifically includes: a bridge arm H1 and a bridge arm H2 connected in parallel, a decoupling capacitor branch formed by two capacitors connected in series, and a resistive load; a decoupling inductor being connected in series between a midpoint of the decoupling capacitor branch and a midpoint of the bridge arm H2.

[0065] A bridge arm H1 of a first device-multiplexing active power decoupling H-bridge unit is sequentially connected in series to an inductor Ls, a resistor Rs, and a power supply Us, and then connected to a bridge arm H2 of a last device-multiplexing active power decoupling H-bridge unit.

[0066] To realize voltage balance of capacitors of the cascaded units when loads are R.sub.1≠R.sub.2≠ . . . ≠R.sub.n, suppress secondary ripple voltage pulsation of a DC bus of a cascaded unit, and ensure that the single-phase cascaded rectifier runs at unit power factors, an integrated control policy of multi-closed-loop multi-objective single-phase cascaded H-bridge rectifier voltage balance and device-multiplexing active power decoupling is provided, which includes three control objectives: first, performing grid-side current control, to implement a unit power factor rectification function; second, performing DC-side voltage equilibration control of the cascaded units, to ensure balance of DC bus voltages of the units when system parameters are inconsistent or the load changes suddenly, so that the system runs stably; third, performing active power decoupling control, to suppress DC-side voltage fluctuations. In a case of the same voltage ripple, a quantity of capacitors connected in parallel to the unit DC bus is reduced by 6 times or more, thereby improving a power density. A control system is shown in FIG. 2, and includes six modules in total: a DC bus voltage control module, a voltage balance control module, a unit power factor rectification module, an active power decoupling control module (for decoupling bridge arm modulation signal generation), a rectification bridge arm modulation signal generation module, and a power switching transistor drive signal generation module. The power switching transistor drive signal generation module includes: a rectification bridge arm drive signal generation module and a decoupling bridge arm drive signal generation module.

[0067] The DC bus voltage control module is configured to add up instantaneous voltages outputted by a controller as a total system voltage through DC-side voltage closed-loop control.

[0068] The voltage balance control module is configured to generate, according to a deviation between an instantaneous voltage P.sub.Vi of each cascaded H-bridge unit and a virtual average voltage, a DC bus voltage deviation modulation signal factor of each cascaded H-bridge unit. P.sub.vi is an instantaneous voltage outputted by a voltage controller.

[0069] The unit power factor rectification module is configured to generate a grid-side current reference value according to the total system voltage, calculate a difference between a grid-side inductor current and the grid-side current reference value, and generate a first modulation signal through a PR controller.

[0070] The active power decoupling control module is configured to generate a reference value of a decoupling inductor current according to an instantaneous power P.sub.n of each cascaded H-bridge unit, calculate a difference between the decoupling inductor current and the reference value of the decoupling inductor current, and generate a modulated wave signal of a bridge arm H2 of each cascaded H-bridge unit through the PR controller. P.sub.n is an instantaneous power of active power decoupling.

[0071] The rectification bridge arm modulation signal generation module is configured to superimpose the modulated wave signal of the bridge arm H2 of each cascaded H-bridge unit onto the first modulation signal and then onto a respective DC bus voltage deviation modulation signal factor, to generate a modulated wave signal of a bridge arm H1 of each cascaded H-bridge unit.

[0072] The rectification bridge arm drive signal generation module is configured to generate a drive signal of the bridge arm H1 of each cascaded H-bridge unit based on the modulated wave signal of the bridge arm H1 of each cascaded H-bridge unit through a carrier phase-shifted modulation technology.

[0073] The decoupling bridge arm drive signal generation module is configured to generate a drive signal of the bridge arm H2 of each cascaded H-bridge unit after comparing the modulated wave signal of the bridge arm H2 of each cascaded H-bridge unit with a carrier signal.

[0074] The working principle of the control system is: adding up, by the DC bus voltage control module, instantaneous voltages P.sub.Vi (i=1, 2, . . . n) outputted by a controller as a total system voltage P.sub.t through DC-side voltage closed-loop control; generating, by the DC-side voltage balance control module, according to a deviation between an instantaneous voltage P.sub.Vi of each cascaded unit and a virtual average voltage P.sub.av (P.sub.av=P.sub.t/n), a respective DC bus voltage deviation modulation signal factor Δm.sub.si; changing, by the unit power factor rectification module, a modulation degree m.sub.sav through a PR controller to control a grid-side inductor current to follow a current reference value i*.sub.s; and generating, by the active power decoupling control module, decoupling inductor current reference values i*.sub.Lr1 and i*.sub.Lr2 according to a real-time power outer loop, control currents of decoupling inductors L.sub.r1 and L.sub.r2 to follow given values, and generate a modulated wave signal of a decoupling bridge arm through the PR controller;

[0075] superimposing, by the rectification bridge arm modulation signal generation module, the modulated wave signal m.sub.sav generated by the unit power factor rectification module onto a signal outputted by an active power decoupling control regulator, modulation signals m.sub.sav1, m.sub.sav2, . . . , and m.sub.savn generated by the two units, and deviation modulation signals Δm.sub.s1 and Δm.sub.s2 generated by the voltage balance module, to finally generate modulation signals m.sub.s1 and m.sub.s2 of the rectification bridge arms.

[0076] The drive signal generation module includes two parts: a rectification bridge arm drive signal and a decoupling bridge arm drive signal. The rectification bridge arm uses a carrier phase-shifted modulation algorithm. A triangular carrier of Bridge n lags 180°/n behind that of Bridge 1, which are compared with a modulated wave to generate a drive signal of a rectification bridge arm of each unit. Under unit power factor rectification conditions, a decoupling capacitor AC voltage component and a grid-side power voltage phase angle θ are determined, decoupling control between units is not affected by unit power factor rectification, power decoupling control between the units has no coupling, and a modulation signal outputted by a decoupling inductor current loop between the units is directly compared with the carrier to generate a decoupling bridge arm drive signal.

[0077] A topology of single-module single-phase device-multiplexing active power decoupling is shown in FIG. 3(a), and an equivalent circuit thereof is shown in FIG. 3(b). It can be learned according to Kirchhoff's law that:

[00001]$\{\begin{array}{c}{L}_s\frac{d{i}_s}{dt}=u_c+u_r+u_s-S_{H1}{u}_{dc}\\ L_r\frac{d{i}_{Lr}}{dt}=u_c-S_{H2}{u}_{dc}\end{array}.$

[0078] It can be seen that in a capacitor-separated decoupling topology, a decoupling unit and a rectification unit share the bridge arm H2, a decoupling inductor current i.sub.Lr is controlled only by the bridge arm H2, and the decoupling inductor Lr and the decoupling capacitor C.sub.u=C.sub.l=C are relatively independent of a grid-side voltage source, which does not affect modular cascade.

[0079] It is assumed that the system works under 50 Hz power frequency conditions. As an inductance value of the inductor L.sub.s is relatively small, a loss thereof is neglected. Moreover, the decoupling capacitor is C.sub.u=C.sub.l=C. Then a secondary ripple power in an input power is shown in formula (1).

P.sub.r=−1/2U.sub.sI.sub.s cos(2ωt)   (1)

[0080] To implement active power decoupling so that an average voltage of the decoupling capacitors is U.sub.dc/2 and superimposed onto a fundamental AC component with a phase difference of 180°, voltages u.sub.cu and u.sub.cl of the decoupling capacitors C.sub.u and C.sub.l may be shown in formulas (2) and (3).

[00002]$\begin{array}{cc}{u}_{cu}=\frac{U_{dc}}{2}+U_c\sin \left(\omega t+\theta \right)& \left(2\right)\\ u_{cl}=\frac{U_{dc}}{2}-U_c\sin \left(\omega t+\theta \right)& \left(3\right)\end{array}$

[0081] In the formulas, U.sub.c is a voltage peak value of an AC component of the decoupling capacitor, and θ is a phase angle between the AC component of the decoupling capacitor voltage and the grid-side voltage.

[0082] Currents i.sub.cu and i.sub.cu flowing through the capacitor are shown in formulas (4) and (5).

[00003]$\begin{array}{cc}{i}_{cu}=C\frac{d{u}_{cu}}{dt}=\omega U_c\cos \left(\omega t+\theta \right)& \left(4\right)\\ i_{cl}=C\frac{d{u}_{cl}}{dt}=-\omega U_c\cos \left(\omega t+\theta \right)& \left(5\right)\end{array}$

[0083] A power p.sub.c generated by the decoupling capacitor is:

P.sub.c=u.sub.cui.sub.cu+u.sub.cli.sub.cl=ωU.sub.c.sup.2 sin(2ωt+2θ)   (6)

[0084] To implement power decoupling, the power p.sub.c of the decoupling capacitor is equal to the secondary ripple power p.sub.r, and the following can be obtained from formulas (6) and (1):

[00004]$\begin{array}{cc}\theta =-\frac{\pi }{4}\mathrm{or}\theta =\frac{3\pi }{4}& \left(7\right)\\ U_c=\sqrt{\frac{U_s{I}_s}{2\omega }}& \left(8\right)\end{array}$

[0085] To determine the phase angle θ, the following analyzes current stress of a power switching device of the bridge arm H2 of the topology, and the decoupling inductor current i.sub.Lr can be obtained by the following formula:

i.sub.Lr=i.sub.cl−i.sub.cu=−2ωU.sub.c cos(ωt+θ)   (9)

[0086] A current i.sub.H2 of a power switching transistor of the bridge arm H2 may be represented as follows:

i.sub.H2=i.sub.s+i.sub.Lr   (10)

[0087] An effective value I.sub.H2 of the current of the power switching transistor of the bridge arm H2 may be represented as follows:

[00005]$\begin{array}{cc}{I}_{H2}=\frac{.Math.i_s+i_{Lr}.Math.}{\sqrt{2}}=\frac{1}{\sqrt{2}}\sqrt{{\left(I_s+2\omega U_c\sin \theta \right)}^2+{\left(2\omega U_c\cos \theta \right)}^2}=\frac{1}{\sqrt{2}}\sqrt{(I_s^2+{\left(2\omega U_c\right)}^2+4\omega U_c{I}_s\sin \theta }& \left(11\right)\end{array}$

[0088] It can be seen from formula (11) that when θ=−π/4, an effective value of the current flowing through the bridge arm H2 switching transistor is relatively small. From the perspective of reducing the current stress of the power device, θ=−π/4.

[0089] θ=−π/4 and formula (8) are substituted into formula (9) to obtain:

[00006]$\begin{array}{cc}{i}_{Lr}=-\sqrt{2\omega U_c{I}_s}\cos \left(\omega t-\frac{\pi }{4}\right)& \left(12\right)\end{array}$

[0090] Then the decoupling inductor current is controlled as shown in formula (12), to implement the active power decoupling control. As analyzed from the perspective of power, formula (12) may be transformed into the following form:

[00007]$\begin{array}{cc}{i}_{Lr}=-2\sqrt{\omega P}\cos \left(\omega t-\frac{\pi }{4}\right)& \left(13\right)\end{array}$

[0091] In the formula, P is (U.sub.sI.sub.s)/2, and is an instantaneous voltage amplitude of the system when the rectifier is actually working. Thus, an active power decoupling control policy based on a combination of closed-loop voltage control and formula calculation is provided, as shown in FIG. 4. The DC bus voltage closed-loop control outputs P representing the instantaneous voltage of the system. The reference value of the decoupling inductor current can be obtained by using formula (13), and then a difference is calculated between the reference value and a decoupling inductor current actually measured by the circuit. A modulation wave is generated by the PR controller. A drive signal of the decoupling bridge arm is generated after the modulation wave is compared with a carrier.

[0092] The single-module active power decoupling system has two control objectives. One is to achieve grid-side inductor current control, that is, to achieve unit power factor rectification; the other is to achieve active power decoupling control. A block diagram of control of a single-module H-bridge device-multiplexing active power decoupling rectifier is shown in FIG. 5. There are four control modules in total: a DC bus voltage control module, a unit power factor rectification control module, an active power decoupling control module, and a drive signal generation module.

[0093] The decoupling inductor current can be controlled only by controlling the H2 bridge arm switching transistor in the topology to be on or off, to realize active power decoupling. In addition, impact of active power decoupling control on the circuit is coupled to unit power factor rectification control, and therefore, a modulation wave of the rectification bridge arm needs to be superimposed onto a modulation wave generated by the active power decoupling control module. In this topology, each modulation wave controls only one bridge arm, and therefore, a modulation method may be unipolar modulation.

Embodiment 2

[0094] In this embodiment, n=2, that is, a single-phase device-multiplexing active power decoupling rectifier includes two device-multiplexing active power decoupling H-bridge units that are cascaded. A control policy thereof is studied, a simulation model is built in Matlab/Simulink, and correctness and effectiveness of the proposed control policy is verified.

[0095] FIG. 6 shows a single-phase CHBR device-multiplexing active power topology with two modules cascaded. The entire system includes two single-phase H-bridge rectifier device-multiplexing active power decoupling units that are cascaded. DC-side capacitors C.sub.u1, C.sub.l1, C.sub.u2, and C.sub.l2 of the units are decoupling capacitors of Bridge 1 and Bridge 2 respectively, u.sub.cu1, u.sub.cl2, u.sub.cu2, and u.sub.cl2 are decoupling capacitor voltages; L.sub.r1 and L.sub.r2 are decoupling inductors, and i.sub.Lr1 and i.sub.Lr2 are currents flowing through the decoupling inductors L.sub.r1 and L.sub.r2; R.sub.1 and R.sub.2 are DC-side resistive loads, and u.sub.dc1 and u.sub.dc2 are DC-side output voltages.

[0096] The single-phase CHBR device-multiplexing active power decoupling system includes three control objectives: first, performing grid-side current control, to implement a unit power factor rectification function; second, performing DC-side voltage equilibration control of the cascaded units, to ensure that the system runs stably when system parameters are inconsistent or the load changes suddenly, which is also a premise for implementation of active power decoupling control function; third, performing active power decoupling control, to suppress DC-side voltage fluctuations.

[0097] A single-phase CHBR device-multiplexing active power decoupling control policy is shown in FIG. 7. The control system includes six modules in total: a DC bus voltage control module, a voltage balance control module, a unit power factor rectification module, an active power decoupling control module (for decoupling bridge arm modulation signal generation), a rectification bridge arm modulation signal generation module, and a power switching transistor drive signal generation module.

[0098] The DC bus voltage control module generates a total system voltage through DC-side voltage closed-loop control, for voltage balance and unit power factor rectification. The DC-side voltage balance module generates respective deviation modulation signal factors based on deviations between an average voltage of the system and virtual instantaneous voltages of the two cascaded units. The unit power factor rectification module controls a grid-side inductor current to follow a current reference value i*.sub.s through a PR controller. The active power decoupling control module generates decoupling inductor current reference values i*.sub.Lr1 and i*.sub.Lr2 based on a power outer loop, controls the currents of the decoupling inductors L.sub.r1 and L.sub.r2 to follow a given value, and generates a modulated wave signal of a decoupling bridge arm. A modulated wave signal of a rectification bridge arm should be superimposed onto the modulated wave signal m.sub.sav generated by the unit power factor rectification module with impact of the active power decoupling control module, to produce modulation signals m.sub.sav1 and m.sub.sav2 of the two units. When parameters of the two units are inconsistent, deviation modulation signals Δm.sub.s1 and Δm.sub.s2 generated by the voltage balance module need to be further superimposed thereon, to finally generate modulation signals m.sub.s1 and m.sub.s2 of the rectification bridge arm. The drive signal generation module includes two parts: a rectification bridge arm drive signal and a decoupling bridge arm drive signal. The rectification bridge arm uses a carrier phase-shifted modulation algorithm. A triangular carrier of Bridge n lags 180°/n behind that of Bridge 1, which are compared with a modulated wave to generate a drive signal of a rectification bridge arm of each unit. Under unit power factor rectification conditions, a decoupling capacitor AC voltage component and a grid-side power voltage phase angle θ are determined, decoupling control between units is not affected by unit power factor rectification, power decoupling control between the units has no coupling, and a modulation signal outputted by a decoupling inductor current loop between the units is directly compared with the carrier to generate a decoupling bridge arm drive signal.

[0099] Simulation analysis of single-phase CHBR system device-multiplexing active power decoupling

[0100] To verify effectiveness of the single-phase CHBR system control policy, a single-phase device-multiplexing active power decoupling simulation model is built in Matlab/Simulink when n=2, that is, when the quantity of cascaded units is 2. The proposed integrated control policy of voltage balance and device-multiplexing active power decoupling is simulated and verified. Simulation parameters are shown in Table 1.

TABLE-US-00001 TABLE 1 Simulation parameters of the single-phase CHBR system Simulation parameter Value Effective value of grid voltage μ.sub.s/V 400 Grid frequency f/Hz 50 Grid inductor L.sub.s/mH 12 Quantity of cascaded units 2 Decoupling capacitor 100 C.sub.u1 C.sub.l1 C.sub.u2 C.sub.l2/uF Decoupling inductor L.sub.r1 L.sub.r2/mH 3 DC-side output voltage 800 U.sub.dc1 U.sub.dc1/V Total output power/kW 8 Switching frequency f.sub.s/kHz 20

[0101] Simulation analysis of load unbalanced startup device-multiplexing active power decoupling

[0102] The simulation process is as follows: When the system starts, DC-side resistive loads are set to R.sub.1=180 Ω and R.sub.2=140 Ω, and therefore, the system starts with unbalanced loads. FIG. 8(a) shows waveforms of DC-side output voltages of two modules, and FIG. 8(b) shows DC-side voltages of the two modules in a time period of 0.9-1.0 s, which achieves a decoupling effect. FIG. 9(a) shows grid-side voltage and current waveforms, and it can be seen from the figure that the system is operating in a unit power factor rectification state. FIG. 9(b) shows a waveform of an input-side voltage U.sub.ab that presents a five-step wave state.

[0103] When the simulation model is built in Simulink, the grid-side voltage is given as u.sub.s=U.sub.s cosωt. According to the single-module analysis process, θ is selected as −3/4π, that is, a phase of a decoupling inductor current lags 3/4π behind a phase of a grid-side current. FIG. 10 shows grid-side current and decoupling inductor current waveforms. It can be seen that the decoupling inductor current i.sub.Lr lags 3/4π behind the grid-side current i.sub.g, which is consistent with the theoretical analysis. FIG. 11 shows waveforms of decoupling capacitor voltages, which are obtained by superimposing a 400 V DC onto voltages with a phase difference of 180°.

[0104] Simulation analysis of device-multiplexing active power decoupling under conditions of sudden load changes

[0105] To verify effectiveness of the control policy when the system is under load unbalanced conditions, a simulation analysis of the system under conditions of load unbalanced start-up and sudden load changes is carried out. FIG. 12 shows waveforms of DC-side output voltages of two modules of an entire simulation process. FIG. 13(a) to FIG. 13(d) show waveforms of simulated DC output voltages of two modules after adjustment and stabilization at each stage. The simulation process is as follows: At the time of system startup, DC-side resistive loads are R.sub.1=200 Ω and R.sub.2=120 Ω, resulting in load unbalanced startup, and DC-side voltages of the two modules are balanced at 0.25 s; R.sub.1 and R.sub.2 both suddenly change to 160 Ω at 0.4 s, and DC-side voltages of the two modules are balanced at 0.7 s; R.sub.1 changes to 200 Ω and R.sub.2 changes to 120 Ω at 0.9 s, and voltages of the two modules are balanced at 0.95 s.

[0106] FIG. 13(a) to FIG. 13(d) show waveforms of simulated DC output voltages of two modules after adjustment and stabilization at each stage. Each simulation stage and DC-side voltage fluctuations of the two modules are analyzed by using FFT of powergui in Simulink. It can be seen from FIG. 12 and FIG. 13(a) to FIG. 13(d) that under the integrated control policy of DC-side voltage balance and device-multiplexing active power decoupling, the system can still implement the DC-side voltage balance and the secondary ripple power suppression under conditions of load unbalanced startup and sudden load changes during system operation, and effectiveness of the proposed control policy is verified.

Embodiment 3

[0107] In one or more implementations, a terminal device is provided, including a server. The server includes a memory, a processor, and a computer program stored in the memory and capable of being run on the processor, and the processor, when executing the program, implements the control policy in Embodiment 1. For brevity, details are not described herein again.

[0108] It should be understood that in this embodiment, the processor may be a central processing unit (CPU); or the processor may be another general purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or another programmable logical device, a discrete gate or a transistor logical device, a discrete hardware component, or the like. The general-purpose processor may be a microprocessor, or the processor may also be any conventional processor or the like.

[0109] The memory may include a read-only memory and a random-access memory, and provide an instruction and data to the processor. A part of the memory may further include a non-volatile random-access memory. For example, the memory may further store information about a device type.

[0110] During implementation, the steps of the foregoing method may be completed through an integrated logic circuit of hardware or an instruction in the form of software in the processor.

[0111] The control policy in Embodiment 1 may be directly performed and completed by a hardware processor, or may be performed and completed by using a combination of hardware in the processor and a software module. The software module may be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, or a register. The storage medium is located in the memory, and the processor reads information in the memory and completes the steps of the foregoing method in combination with the hardware in the processor. To avoid repetition, details are not described herein again.

[0112] A person of ordinary skill in the art may notice that the exemplary units and algorithm steps described with reference to this embodiment can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical scheme. A person skilled in the art may use different methods to implement the described functions for each particular application, but it is not to be considered that the implementation goes beyond the scope of this application.

[0113] The specific implementations of the present invention are described above with reference to the accompanying drawings, but are not intended to limit the protection scope of the present invention. Those skilled in the art should understand that various modifications or deformations may be made without creative efforts based on the technical solutions of the present invention, and such modifications or deformations shall fall within the protection scope of the present invention.