STORAGE STRUCTURE AND ERASE METHOD THEREOF

Abstract

The invention provides a storage structure and an erase method thereof, which can perform an erase operation on memory blocks B.sub.1 . . . B.sub.n, where n is an integer greater than or equal to 2. The storage structure includes a first memory bank, a second memory bank and a controller, wherein the memory blocks are sequentially alternately arranged in the first memory bank and the second memory bank. The controller is used to control the memory blocks to sequentially undergo an erase operation. The erase operation includes sequentially performing a first process and a second process. When memory block B.sub.i undergoes the second process, the memory block B.sub.i+1 undergoes the first process, where i ∈ [1, n−1].

Claims

1. A storage structure capable of performing an erase operation on memory blocks B.sub.1 . . . B.sub.n, where n is an integer greater than or equal to 2, the storage structure comprising a first memory bank, a second memory bank, and a controller, wherein the memory blocks are sequentially alternately arranged in the first memory bank and the second memory bank, and the controller is configured to control the memory blocks to undergo an erase operation, wherein the erase operation comprises sequentially performing a first process and a second process; wherein when memory block B.sub.i undergoes the second process, the memory block B.sub.i+1 undergoes the first process, where i ∈ [1, n−1].

2. The storage structure according to claim 1, wherein after the memory block B.sub.1 completes the first process, the memory block B.sub.1 undergoes the second process and the memory block B.sub.2 undergoes the first process at the same time; then the erase operation is performed on the remaining memory blocks sequentially until the memory block B.sub.i+1 undergoes the second process and the memory block B.sub.n undergoes the first process at the same time, then the memory block B.sub.n undergoes the second process.

3. The storage structure according to claim 1, wherein the first process includes a pre-programming step and an erase step, and the second process includes an over-erase correction step, wherein the erase step is performed after the pre-programing step.

4. The storage structure according to claim 1, wherein the first erase step includes a pre-programming step, and the second process includes an erase step and an over-erase correction step, wherein the over-erase correction step is performed after the erase step.

5. The storage structure according to claim 1, wherein the numbers of memory blocks in the first memory bank and the second memory bank are the same or different.

6. The storage structure according to claim 1, wherein the storage structure comprises M memory banks, wherein M is greater than or equal to 2.

7. The storage structure according to claim 1, wherein the controller comprises: a first memory bank controller, coupled to the first memory bank for controlling the first memory bank; a second memory bank controller, coupled to the second memory bank for controlling the second memory bank; a chip controller coupled to the first memory bank controller and the second memory bank controller and capable of simultaneously operating on the memory blocks in the first memory bank and the second memory bank.

8. The storage structure according to claim 1, wherein the storage structure is a Nor flash.

9. A method of erasing a storage structure, used to perform an erase operation on memory blocks B.sub.1 . . . B.sub.n, where n is an integer greater than or equal to 2, and the method comprises: sequentially alternately arranging the memory blocks in the first memory bank and the second memory bank; and controlling the memory blocks to sequentially undergo an erase operation; wherein the erase operation includes sequentially performing a first process and a second process, and when a memory block B.sub.i undergoes the second process, a memory block B.sub.i+1 undergoes the first process, wherein, i ∈ [1, n−1].

10. The method for erasing a storage structure according to claim 9, wherein the method for erasing the storage structure is used for entire erasing of the storage structure.

11. The storage structure according to claim 2, wherein the first process includes a pre-programming step and an erase step, and the second process includes an over-erase correction step, wherein the erase step is performed after the pre-programing step.

12. The storage structure according to claim 2, wherein the first erase step includes a pre-programming step, and the second process includes an erase step and an over-erase correction step, wherein the over-erase correction step is performed after the erase step.

13. The storage structure according to claim 2, wherein the numbers of memory blocks in the first memory bank and the second memory bank are the same or different.

14. The storage structure according to claim 2, wherein the storage structure comprises M memory banks, wherein M is greater than or equal to 2.

15. The storage structure according to claim 7, wherein the storage structure is a Nor flash.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG. 1 is a schematic structural diagram of a storage structure according to the related art.

[0028] FIG. 2 is a flowchart of the erase method of the storage structure in FIG. 1.

[0029] FIG. 3 is a schematic structural diagram of a storage structure according to a first embodiment of the present invention.

[0030] FIG. 4 is a flowchart of a method for erasing a storage structure according to a first embodiment of the present invention.

[0031] FIG. 5 is a flowchart of a method for erasing a storage structure according to a second embodiment of the present invention.

DETAILED DESCRIPTION

[0032] The specific embodiments of the present invention will be described in more detail below with reference to the schematic diagrams. The advantages and features of the invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and all use inaccurate proportions, which are only used to facilitate and clearly assist the description of the embodiments of the present invention. The numbers of the memory blocks and banks are intended to aid explanation of the scheme, and it does not mean that the corresponding numbers of the memory blocks and the banks must be set as in the figures, nor does it mean that the numbering of the blocks must be in accordance with the numbering method in order to realize this invention.

EMBODIMENT I

[0033] FIG. 3 is a schematic structural diagram of a storage structure provided by this embodiment. The storage structure 300 is, for example, a Nor Flash, which includes at least two banks, namely a first bank Bank2 and a second bank Bank3. The first bank Bank2 and the second bank Bank3 store a total of n (n≥2) memory blocks, and the n memory blocks are evenly distributed in the first bank Bank2 and the second bank Bank3. The memory blocks therein are alternately arranged in the first bank Bank2 and the second bank Bank3 according to the numbering sequence. For ease of description, the n memory blocks are sequentially numbered as: B.sub.1, B.sub.2 . . . B.sub.n. In this embodiment, n is an even number. In this way, the memory blocks B.sub.1, B.sub.3 . . . B.sub.n−1 are arranged in the first memory Bank2, and the memory blocks B.sub.2, B.sub.4 . . . B.sub.n are arranged in the second memory Bank3. At this time, the numbers of the memory blocks stored in the first bank Bank2 and the second bank Bank3 are the same.

[0034] Obviously, when n is an odd number, there will be one more memory block stored in the first memory bank Bank2 than the second memory bank Bank3, but this does not affect the implementation of the present invention.

[0035] The storage structure 300 further includes a controller, which comprises a chip controller 210, a first memory bank controller 220 and a second memory bank controller 230. The first memory bank controller 220 is connected to and controls the first memory bank Bank2, while the second memory bank controller 230 is connected to and controls the second memory bank Bank3. The chip controller 210 is coupled to the first memory bank controller 220 and the second memory bank controller 230 and is configured to control the first memory bank Bank2 and the second memory bank Bank3 to perform operations such as read, write, and erase. Because addresses of the first memory bank Bank2 and the second memory bank Bank3 and corresponding bias conditions (voltages required to be applied to the source, drain, or gate) are different, this embodiment relies on the chip controller 210 to control both the first memory bank controller 220 and the second memory bank controller 230. The first memory bank controller 220 and the second memory bank controller 230 control the first memory bank Bank2 and the second memory bank Bank3, respectively, such that the chip controller 210 can simultaneously perform operations upon the memory blocks in the first memory bank Bank2 and the second memory bank Bank3.

[0036] It should be understood, however, that according to existing integrated circuit design and manufacturing technologies, the first memory bank controller 220, the second memory bank controller 230, and the chip controller 210 may be integrated into a single control unit, or may be modularized as two, four, or multiple control units. This should be understood by those skilled in the art. The embodiment detailed here merely provides a preferred solution.

[0037] This embodiment also provides an erase method of the storage structure 300, which is used to perform entire erasing of the storage structure 300. Specifically, the memory blocks are sequentially alternately arranged in the first memory bank Bank2 and the second memory bank Bank3. When the storage structure 300 needs to be erased entirely, the controller controls the memory blocks B.sub.1, B.sub.2 . . . B.sub.n to sequentially undergo an erase operation, wherein the erase operation includes a first process and a second process. When the first process and the second process have both been performed on a memory block, the erase operation is completed for the memory block. When the memory block B.sub.i undergoes the second process, the memory block B.sub.i+1 undergoes the first process, where i ∈ [1, n−1]. In other words, for the two adjacent memory blocks, memory block B.sub.1 undergoes the second process and memory block B.sub.i+1 undergoes the first process simultaneously. After the memory block B.sub.i completes the second process and the memory block B.sub.i+1 completes the first process, the erasing of the memory block B.sub.i is completed; then, the memory block B.sub.i+1 undergoes the second process, and simultaneously the memory block B.sub.i+2 undergoes the first process. This continues in a pipeline manner until the erasing of the memory block B.sub.n is completed, thereby entirely erasing the storage structure 300.

[0038] In this embodiment, the first process includes a pre-programing step, while the second process includes an erase step and an over-erase correction step (OEC), which must be performed sequentially.

[0039] FIG. 4 is a flowchart 400 of the erase method of the storage structure 300 according to this embodiment. The erase method of the storage structure 300 provided in this embodiment will be described in detail with reference to FIGS. 3 and 4.

[0040] As shown in FIG. 4, the memory block B.sub.1 first undergoes a pre-programming step (first process); after the memory block B.sub.1 completes the pre-programming step, the memory block B.sub.1 undergoes an erase step followed by an over-erase correction step. At the same time, the memory block B.sub.2 undergoes a pre-programming step. After the memory block B.sub.1 completes the erase step and the over-erase correction step, the erasing of the memory block B.sub.1 is completed (B.sub.1 Erase Done). The memory block B.sub.2 has also completed the pre-programming step, and will then undergo the erase step as well as the over-erase correction step, while the memory block B.sub.3 undergoes the pre-programming step. After the memory block B.sub.2 completes the erase step and the over-erase correction step, the erasing of the memory block B.sub.2 is completed (B.sub.2 Erase Done). At the same time, the memory block B.sub.3 completes the pre-programming step. These steps will be sequentially performed until the memory block B.sub.n−1 has completed the erase step and the over-erase correction step and the memory block B.sub.n has completed the pre-programming step, so the erasing of the memory block B.sub.n−1 is completed (B.sub.n−1 Erase Done). To complete entire erasing of the storage structure, the memory block B.sub.n needs to undergo the erase step and the over-erase correction step.

[0041] The erase method shown in FIG. 2 requires each memory block to complete its erase operation separately before a next memory block begins its erase operation. In the embodiment shown in FIG. 4, because the memory block B.sub.i undergoes the second process and the memory block B.sub.i+1 undergoes the first process simultaneously, erasing time is saved, which improves erasing efficiency.

[0042] In order to prove that the erase method of the storage structure provided in this embodiment improves the erasing efficiency, the following assumptions and calculations are made:

[0043] Assume n=256, the time of the pre-programming step t1=50 ms, the time of the erase step t2=80 ms, and the time of the over-erase repair step t3=20 ms;

[0044] The time T1 required to erase the entire storage structure by using the erase method shown in FIG. 2 is:

T1=(50 ms+80 ms+20 ms)*256=38.4 s

[0045] The time T2 required to erase the entire storage structure by using the erase method shown in FIG. 4 is:

T2=((80 ms+20 ms)*256)+50 ms=25.65 s

[0046] It can be seen that, compared with the erase method of the storage structure provided in FIG. 2, the erase method of the storage structure provided by this embodiment can improve the erasing efficiency by about 33.2%.

EMBODIMENT II

[0047] In this embodiment, the first process includes a pre-programming step and an erase step, while the second process includes an over-erase correction step. When the memory block B.sub.i undergoes the second process, only the over-erase correction step is performed. When the memory block B.sub.i+1 undergoes the first process, the pre-programming step and the erase step are sequentially performed.

[0048] FIG. 5 is a flowchart 500 of the erase method of the storage structure 300 according to this embodiment. The erase method of the storage structure 300 provided in this embodiment will be described in detail with reference to FIGS. 3 and 5.

[0049] As shown in FIG. 5, first, the memory block B.sub.1 sequentially undergoes the pre-programming step and the erase step; after the memory block B.sub.1 completes the pre-programming step and the erase step, the memory block B.sub.1 undergoes the over-erase correction step, while the memory block B.sub.2 sequentially undergoes a pre-programming step and an erase step; after the memory block B.sub.1 completes the over-erase correction step and the memory block B2 completes the pre-programming step and the erase step, the erasing of the memory block B.sub.1 is completed (B.sub.1 Erase Done). Next, the memory block B.sub.2 undergoes the over-erase correction step, and the memory block B.sub.3 undergoes the pre-programming step and the erase step; after the memory block B.sub.2 completes the over-erase correction step and the memory block B.sub.3 completes the pre-programming step and erase step, the erasing of the memory block B.sub.2 is completed (B.sub.2 Erase Done). Then, these steps are sequentially performed until the memory block B.sub.n−1 has completed the over-erase correction step and the memory block B.sub.n has completed the pre-programming step and the erase step. Then, the erasing of the memory block B.sub.n−1 is completed (B.sub.n−1 Erase Done). The memory block B.sub.n needs to undergo the over-erase correction step separately. After the memory block B.sub.n completes the over-erase correction step, the erasing of the memory block B.sub.n is completed (B.sub.n Erase Done), and the storage structure 200 has completed the entire erasing.

[0050] In order to prove that the erase method of the storage structure provided in this embodiment improves the erasing efficiency, the same assumptions and calculations as those in the first embodiment are made:

[0051] Assume n=256, the time of the pre-programming step t1=50 ms, the time of the erase step t2=80 ms, and the time of the over-erase repair step t3=20 ms;

[0052] The time T2 required to erase the entire storage structure by using the erase method of the storage structure provided in FIG. 5 is:

T2=(50 ms+80 ms)*256+20 ms=33.3 s

[0053] It can be seen that, compared with the erase method of the storage structure provided in FIG. 2, the erase method of the storage structure provided by this embodiment can improve the erasing efficiency by about 13.3%.

[0054] The saved erasing time calculated with reference to Embodiments I and II are reference values. The flash memory may have different pre-programming time, erasing time, and over-erase correction time depending on the manufacturing process and operation mode. Therefore, the erasing time saved in the embodiment II is not necessarily the same, and may be lower than in Embodiment I.

[0055] In addition, the number of banks in Embodiments I and II is not limited to two, and may be M, where M is preferably a multiple of 2. When M is not a multiple of 2, the present invention can also be implemented by applying the inventive method to most memory banks in a storage structure.

[0056] In summary, in the storage structure and the erase method provided by the embodiments of the present invention, an erasing operation can be performed on sequentially numbered memory blocks B.sub.1 . . . B.sub.n, where n is an integer greater than or equal to 2, and the storage structure includes a first memory bank, a second memory bank, and a controller, wherein the memory blocks are sequentially alternately stored in the first memory bank and the second memory bank, and the controller is used to control the memory blocks. The erase operation is performed sequentially on the memory blocks, and includes a first process and a second process. The erasing operation comprises the memory block B.sub.i undergoing the second process while the memory block B.sub.i+1 undergoes the first process, where i ∈ [1, n−1]. Erasing time of the entire erasing of the storage structure is saved, which improves the erasing efficiency, while requiring no additional circuits.

[0057] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.