POWER CONVERTER AND METHOD OF ENTERING SKIP AT A FIXED OUTPUT POWER IN A LIGHT LOAD CONDITION INDEPENDENT OF MAGNETIZING INDUCTANCE

Abstract

A power converter has a power transistor and inductor coupled in a conduction path with the power transistor. A switching frequency of the power transistor is reduced during a light load condition. A pulse width of a drive signal to the power transistor is controlled to select a current through the inductor and power transistor corresponding to the switching frequency to maintain a fixed output power of the power converter, and further to vary the current through the inductor and power transistor to maintain the fixed output power of the power converter over a range of switching frequencies. A first number of pulses of the drive signal to the power transistor during a first time period sets the fixed output power of the power converter. No pulses of the drive signal are provided during a second time period after the first time period.

Claims

1. A method of maintaining a fixed output power during a light load condition in a power converter, comprising: providing a power device; reducing a switching frequency of the power device during the light load condition; and controlling a pulse width of a drive signal to the power device to vary a current through the power device to maintain the fixed output power of the power converter over a range of switching frequencies.

2. The method of claim 1, further including measuring a value of the current through the power device to control the pulse width of the drive signal to the power device.

3. The method of claim 1, further including: providing a first number of pulses of the drive signal to the power device during a first time period to set the fixed output power of the power converter; and providing no pulses of the drive signal during a second time period after the first time period.

4. The method of claim 3, further including: providing a second number of pulses of the drive signal to the power device during a third time period after the second time period to set the fixed output power of the power converter, wherein the second number of pulses is different from the first number of pulses; and providing no pulses of the drive signal during a fourth time period after the third time period.

5. The method of claim 1, further including: setting the switching frequency of the power device to different values in response to different loads on the power converter; and varying the current through the power device to maintain the fixed output power of the power converter for the different values of the switching frequency.

6. The method of claim 1, wherein the current through the power device varies with the switching frequency.

7. A method of maintaining a fixed output power during a light load condition in a power converter, comprising: providing a semiconductor device; reducing a switching frequency of the semiconductor device during the light load condition; and controlling a pulse width of a drive signal to the semiconductor device to select a current through the semiconductor device corresponding to the switching frequency to maintain the fixed output power of the power converter.

8. The method of claim 7, further including controlling the pulse width of the drive signal to the transistor to vary the current through the semiconductor device to enter a fixed power delivery point at the same output power over a range of switching frequencies.

9. The method of claim 7, further including measuring a value of the current through the semiconductor device to control the pulse width of the drive signal to the semiconductor device.

10. The method of claim 7, further including: providing a first number of pulses of the drive signal to the semiconductor device during a first time period to set the fixed output power of the power converter; and providing no pulses of the drive signal during a second time period after the first time period.

11. The method of claim 10, further including: providing a second number of pulses of the drive signal to the semiconductor device during a third time period after the second time period to set the fixed output power of the power converter, wherein the second number of pulses is different from the first number of pulses; and providing no pulses of the drive signal during a fourth time period after the third time period.

12. The method of claim 7, further including: setting the switching frequency of the device to different values in response to different loads on the power converter; and varying the current through the semiconductor device to maintain the fixed output power of the power converter for the different values of the switching frequency.

13. The method of claim 7, wherein the current through the semiconductor device varies with the switching frequency.

14. A power converter having a fixed output power during a light load condition, comprising: a semiconductor device; means for reducing a switching frequency of the semiconductor device during the light load condition; and means for controlling a pulse width of a drive signal to the semiconductor device to select a current through the semiconductor device corresponding to the switching frequency to maintain the fixed output power of the power converter.

15. The power converter of claim 14, further including means for controlling the pulse width of the drive signal to the semiconductor device to vary the current through the semiconductor device to maintain the fixed output power of the power converter over a range of switching frequencies and hence a range of primary inductances.

16. The power converter of claim 14, further including means for measuring a value of the current through the semiconductor device to control the pulse width of the drive signal to the device.

17. The power converter of claim 14, further including means for providing a first number of pulses of the drive signal to the semiconductor device during a first time period to set the fixed output power of the power converter, and providing no pulses of the drive signal during a second time period after the first time period.

18. The power converter of claim 17, further including means for providing a second number of pulses of the drive signal to the semiconductor device during a third time period after the second time period to set the fixed output power of the power converter, wherein the second number of pulses is different from the first number of pulses, and providing no pulses of the drive signal during a fourth time period after the third time period.

19. The power converter of claim 14, further including: means for setting the switching frequency of the semiconductor device to different values in response to different loads on the power converter; and means for varying the current through the semiconductor device to maintain the fixed output power of the power converter for the different values of the switching frequency.

20. The power converter of claim 14, wherein the current through the semiconductor device varies with the switching frequency.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 illustrates a graph of primary inductance versus oscillator switching frequency with a fixed primary inductor current;

[0009] FIG. 2 illustrates a graph of output power versus primary magnetized inductance with a fixed primary inductor current while operating in PFM;

[0010] FIG. 3 illustrates a schematic and block diagram of an ACF power converter;

[0011] FIG. 4 illustrates a graph of output power or peak primary inductor current versus primary inductance;

[0012] FIG. 5 illustrates operation of the ACF power converter over time;

[0013] FIG. 6 illustrates a graph of measured primary inductor current and power transistor on-time versus primary inductance; and

[0014] FIG. 7 illustrates a circuit to vary the primary inductor current with the switching frequency.

DETAILED DESCRIPTION OF THE DRAWINGS

[0015] The following describes one or more embodiments with reference to the figures, in which like numerals represent the same or similar elements. While the figures are described in terms of the best mode for achieving certain objectives, the description is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the disclosure. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.

[0016] FIG. 3 is a schematic and block diagram of active clamp flyback (ACF) power converter 100. ACF power converter or controller 100 is implemented on a semiconductor die and packaged with an encapsulation and external leads electrically connected to certain circuit nodes. A DC input voltage V.sub.IN is applied at terminal 102 as a first external lead of the semiconductor package, which is coupled to a first terminal of inductor 104. Inductor 104 is an input or primary side of transformer 106 and inductor 108 is an output or secondary side of the transformer, shown with polarity dots 110. Inductor 104 has an inductance, referred to as primary inductance, which is a function of switching frequency f.sub.O. The primary inductance may range, but not limited, from 50 micro-henries (μh) to 1.2 milli-henries (mh). The DC input voltage V.sub.IN is further applied through capacitor 112 to the drain of power transistor 114. The source of power transistor 114 is coupled to the drain of power transistor 116 at node 118. The source of power transistor 116 is coupled through resistor 120 to power supply terminal 122 as a second external lead of the semiconductor package operating at ground potential. A primary inductor current I.sub.PRI flows through inductor 104, given the input voltage V.sub.IN, when power transistor 116 is in a conductive state. Accordingly, inductor 104 is coupled in a conduction path of power transistor 116. A current sense (CS) voltage develops across resistor 120 at node 124 from the primary inductor current I.sub.PRI flowing through power transistor 116. In one embodiment, transistors 114 and 116 are power MOSFETs and each include an internal body diode 126 and 128, respectively. A second terminal of inductor 104 is coupled to node 118. A first terminal of inductor 106 is coupled through diode 130 to output terminal 132, and a second terminal of inductor 106 is coupled to power supply terminal 122. Capacitor 136 is coupled between output terminal 132 and power supply terminal 122. Output terminal 132 provides a regulated DC output voltage V.sub.OUT during steady-state operation of ACF power converter 100.

[0017] The regulation of V.sub.OUT is achieved with high side driver (HDRV) control circuit 140 and PWM and low side driver (PWM/LDRV) control circuit 142. HDRV 140 has first and second outputs coupled to the gates of push-pull transistors 144 and 146. The source of transistor 144 and drain of transistor 146 are coupled to the gate of power transistor 114 at node 150. The source of transistor 146 is coupled to node 118, and the drain of transistor 144 is coupled to node 154. Node 154 provides operating potential to the drain of transistor 144. HDRV 140 controls power transistor 114 through push-pull transistors 144 and 146. PWM/LDRV 142 has first and second outputs coupled to the gates of push-pull transistors 160 and 162. The source of transistor 160 and drain of transistor 162 are coupled to the gate of power transistor 116 at node 164. The source of transistor 162 is coupled through resistor 120 to ground terminal 122. Node 124 is also coupled to PWM/LDRV 142. Current source 174 is coupled to V.sub.IN and provides current I.sub.IN to generate operating potential V.sub.DD at the drain of transistor 160, as well as PWM/LDRV 142. PWM/LDRV 142 controls power transistor 116 through push-pull transistors 160 and 162. Capacitor 170 is coupled between node 154 and node 118. Capacitor 172 is coupled between the drain of transistor 160 and ground terminal 122. Programmable oscillator 176 provides a user selectable oscillator frequency f.sub.O to HDRV 140 and PWM/LDRV 142. Resistor 180 is coupled to programmable oscillator 176. A value of resistor 180 selects a normal or maximum switching frequency of oscillator 176 from 100 kHz to 1 MHz. Oscillator 176 is programmable to a range of frequencies less than the normal or maximum switching frequency set by resistor 180.

[0018] In steady state operation of ACF power converter 100, HDRV 140 and PWM/LDRV 142 provide pulses to switch (turn on and turn off) power transistors 114 and 116 in sequence to store energy in inductor 104 and then transfer that energy to inductor 106 and output terminal 132 as output voltage V.sub.OUT. HDRV 140 and PWM/LDRV 142 operate with the oscillator switching frequency f.sub.O to deliver variable duty cycle pulses to enable transistors 144-146 and transistors 160-162 to drive the gates of power transistors 114 and 116, respectively. The oscillator switching frequency f.sub.O is selectable, say from 100 kHz to 1 MHz, and the duty cycle of the pulses is controlled with feedback circuit 182 from output terminal 132 back to inputs of HDRV 140 and PWM/LDRV 142. The duty cycle of the pulses from HDRV 140 and PWM/LDRV 142 to power transistors 114 and 116 is controlled by feedback circuit 182 to regulate V.sub.OUT under varying loads and input voltage conditions.

[0019] Regulatory authorities establish requirements on power converter standby power and light load efficiency. As the load decreases below a threshold, say 50% of full load, the oscillator switching frequency f.sub.O is decreased in a controlled fashion, i.e., in frequency fold-back mode, to reduce the switching losses and improve overall efficiency of the power converter. As the load decreases below 5% of full load, i.e., a light load or no-load condition, the frequency fold-back operation typically reduces f.sub.O to a minimum switching frequency of about 25 kHz. A frequency clamp is typically activated at 25 kHz to ensure that the switching frequency remains above the audible range, i.e., 22 kHz.

[0020] Under a light load or no-load condition, the output power P.sub.O delivered by ACF power converter 100 operating in DCM is given in equation (1) as:

P.sub.O=0.5*L.sub.PRI*I.sub.PRI.sup.2*f.sub.O  (1) [0021] where: L.sub.PRI is primary inductance of inductor 104 [0022] I.sub.PRI is primary current through inductor 104 [0023] f.sub.O is switching frequency of oscillator 176

[0024] The value of resistor 180 sets the normal or maximum switching frequency of oscillator 176 from 100 kHz to 1 MHz. Oscillator 176 is programmed to lower values during times of decreasing load. During the light load or no-load condition of interest, i.e., less than 5% of full load, the switching frequency f.sub.O is set to 25 kHz. Primary inductance is a function of switching frequency, so the frequency set by the oscillator f.sub.O sets the primary inductance. At the light load or no-load switching frequency of 25 kHz, ACF power converter provides a fixed or constant output power, say P.sub.O=2.0 watts, in order to achieve the target standby power and light load efficiency. In order to make the output power P.sub.O relatively constant during light load or no-load conditions, the primary inductor current I.sub.PRI is varied over a range of switching frequencies and associated primary inductances. FIG. 4 illustrates the values of primary inductor current I.sub.PRI, shown as line 192, over a range of primary inductance values that result in a fixed output power P.sub.O. FIG. 4 further illustrates the fixed output power of ACF power converter 100, shown as line 190, over the range of primary inductance values. In other words, the output power in line 190 remains fixed and constant by varying the values of frozen primary inductor current during foldback according to line 192 over a range of switching frequencies and associated primary inductances. Given a specific switching frequency and associated primary inductance, the proper peak primary inductor current I.sub.PRI is selected in accordance with line 192 to achieve a fixed output power P.sub.O in line 190. In one embodiment, ACF power converter 100 provides a fixed 2.0 watts of output power P.sub.O by varying the primary inductor current I.sub.PRI according to line 192 over a range of switching frequencies and associated primary inductances.

[0025] FIG. 5 illustrates operation of ACF power converter 100 with varying loads over time. Given a light load or no-load condition at time t.sub.1, PWM/LDRV 142 turns on transistor 160 which provides a high drive signal to the gate of power transistor 116 (gate voltage goes high) to turn on the power transistor. The conduction of power transistor 116 causes the primary inductor current I.sub.PRI to flow through inductor 104 which stores energy in the inductor. The primary inductor current I.sub.PRI is measured as a voltage across resistor 120. The voltage at node 124 is routed to PWM/LDRV 142. The PWM control circuit detects when the primary inductor current I.sub.PRI reaches the value in accordance with line 192 for the primary inductance at 25 kHz by comparing the primary inductor current I.sub.PRI as measured across resistor 120 and to internally stored table of values corresponding to line 192. PWM/LDRV 142 turns on transistor 162 which provides a low drive signal to the gate of power transistor 116 (gate voltage goes low) to turn off the power transistor, thus defining the first pulse width of the drive signal for the node 164 waveform in FIG. 5. During the off-time of power transistor 116 immediately after the first pulse, the energy stored in inductor 104 is transferred to inductor 106, which increases the output voltage V.sub.OUT. The switching (turn on and turn off) of power transistor 116 occurs for a second pulse width of the drive signal, and a third pulse width of the drive signal, and so on, as shown between times t.sub.1-t.sub.2, with a switching frequency f.sub.O=25 kHz. Each pulse width is set according to the on-time of power transistor 116 needed to reach the primary inductor current I.sub.PRI in accordance with line 192, given the switching frequency f.sub.O. In one embodiment, the pulse width of the drive signal ranges from 200-500 nanoseconds (ns) to reach the primary inductor current I.sub.PRI in line 192. The output voltage V.sub.OUT increases with each energy storage and transfer cycle associated with each pulse at node 164. The number of pulses is determined by feedback circuit 182. When the output voltage V.sub.OUT reaches its regulation value, feedback circuit 182 signals PWM/LDRV 142 to stop generating pulses and turn on transistor 162 to maintain power transistor 116 in a non-conductive state. In a light load or no-load condition, PWM/LDRV 142 typically generates 3-5 pulses between times t.sub.1-t.sub.2.

[0026] FIG. 6 illustrates a graph of primary inductor current I.sub.PRI and power transistor 116 on-time versus primary inductance. The primary inductor current I.sub.PRI decrease with increasing primary inductance. The on-time of power transistor 116 increases with increasing primary inductance.

[0027] PWM/LDRV 142 generates no pulses between times t.sub.2-t.sub.3, see the node 164 waveform in FIG. 5. The time period t.sub.2-t.sub.3 of no pulses is referred to as pulse skipping period or sleep time, with a duration of 100-300 milliseconds (ms). Power transistor 116 remains in a non-conductive state during pulse skipping period and no energy is delivered to the secondary side of transformer 108. The output voltage V.sub.OUT decreases under the light load or no-load condition between times t.sub.2-t.sub.3. When the output voltage V.sub.OUT decreases to a minimum regulation threshold, the above process repeats with a series of pulses between times t.sub.3-t.sub.4, followed by another pulse skipping period between times t.sub.4-t.sub.5. Again, each pulse width is set according to the on-time of power transistor 116 needed to reach primary inductor current I.sub.PRI in accordance with line 192, given the switching frequency f.sub.O. The cycle continues for the duration of the light load or no-load condition.

[0028] Variations in load, even within a light load state, are handled by the number of pulses needed to maintain regulation of V.sub.OUT. The greater the load, the greater the number of pulses in order to maintain regulation of V.sub.OUT. The time period t.sub.5-t.sub.6 illustrates a light load state with a greater number of pulses to maintain regulation of V.sub.OUT. Each pulse width is set according to the on-time of power transistor 116 needed to reach primary inductor current I.sub.PRI in accordance with line 192, given the switching frequency f.sub.O in the light load state.

[0029] As the load increases above a light load condition at time t.sub.6, i.e., greater than 5% of full load, the switching frequency may increase above 25 kHz. During times t.sub.6-t.sub.7, the number of pulses, width of the pulses, the length of the pulse skipping period, and the switching frequency f.sub.O is determined by the energy transfer across transformer 108 needed to maintain regulation of V.sub.OUT. Again, each pulse width is set according to the time needed to reach primary inductor current I.sub.PRI in accordance with line 192, given the primary inductance associated with the higher switching frequency f.sub.O. The number of pulses and the length of the pulse skipping period, given the higher switching frequency f.sub.O, regulates the output voltage V.sub.OUT. As the load on ACF power converter 100 continues to increase toward full load, pulse skipping ceases, as shown at time t.sub.7, and normal PWM regulation returns for ACF power converter 100.

[0030] FIG. 7 illustrates a circuit to vary the primary inductor current with the switching frequency. Circuit 220 detects a switching frequency dependent threshold of primary inductor current I.sub.PRI and sends a signal to PWM/LDRV 142 to end the pulse and turn off power transistor 116. An inverting input of amplifier 222 is coupled to node 124 to receive a voltage representative of primary inductor current I.sub.PRI. Current source 224 provides a current proportional to the switching frequency f.sub.O of oscillator 176. Current source 224 is coupled to resistor 226 to generate a reference voltage at the non-inverting input of amplifier 222 proportional to the switching frequency f.sub.O of oscillator 176. The output of amplifier 222 is coupled to PWM/LDRV 142. At time t.sub.1 in FIG. 5, PWM/LDRV 142 turns on transistor 160, which in turn enables power transistor 116 to conduct primary inductor current I.sub.PRI. When the primary inductor current I.sub.PRI exceeds the reference voltage across resistor 226, which is proportional to the switching frequency f.sub.O, the output of amplifier 222 causes PWM/LDRV 142 to end the pulse by turning on transistor 162 and turning off power transistor 116. Accordingly, PWM/LDRV 142 generates a pulse at node 164 that is a function of the switching frequency f.sub.O, which causes the primary inductor current I.sub.PRI to vary with the switching frequency f.sub.O. The lower the switching frequency f.sub.O, the lower the primary inductor current I.sub.PRI, and the higher the switching frequency f.sub.O, the higher the primary inductor current I.sub.PRI.

[0031] While one or more embodiments have been illustrated and described in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present disclosure.