InP-based transistor fabrication

Abstract

Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

Claims

1. A method of fabricating a transistor, the method comprising: providing an InP-based material layer structure including a channel layer; passivating the InP-based material layer structure with sulfur; forming a protection dielectric layer over the passivated InP-based material layer structure; forming a source region and a drain region in the passivated InP-based material layer structure using implantation of dopants through the protection dielectric layer; providing a channel region between the source and drain regions, the channel region including at least a portion of the channel layer; after forming the source region and the drain region, completely removing the protection dielectric layer; after completely removing the protection dielectric layer, removing a native oxide from the passivated InP-based material layer structure using an in situ gas-phase cleaning process; after removing the native oxide from the passivated InP-based material layer structure, depositing a gate dielectric over the passivated InP-based material layer structure including the channel region by atomic layer deposition (ALD); and providing a gate above the channel region, wherein at least a portion of the gate dielectric is disposed between the gate and the channel region.

2. The method of claim 1 wherein the source and drain regions are at least partially disposed in the channel layer.

3. The method of claim 1 wherein the source and drain regions are disposed above the channel layer.

4. The method of claim 1 wherein the gate dielectric comprises at least one of a group II material or a transition metal.

5. The method of claim 4 wherein the gate dielectric comprises aluminum.

6. The method of claim 4 wherein the gate dielectric comprises hafnium.

7. The method of claim 1 wherein the channel layer comprises a strained region.

8. The method of claim 1 wherein the channel layer comprises at least one of InSb, InGaAs, InAs, or InP.

9. The method of claim 1 wherein the channel layer comprises a plurality of substantially lattice-matched layers.

10. The method of claim 1 wherein the transistor is a MOSFET.

11. The method of claim 1 further comprising: providing a silicon substrate, wherein the InP-based material layer structure is provided over the silicon substrate.

12. The method of claim 1, wherein the in situ gas-phase cleaning process is performed using a HF-based gas, a HCl-based gas, or a combination thereof.

13. A method of fabricating a semiconductor structure, the method comprising: providing a semiconductor layer comprising indium and phosphorous; cleaning and passivating the semiconductor layer; after cleaning and passivating the semiconductor layer, depositing by ALD, above at least a portion of the semiconductor layer, a dielectric layer comprising hafnium; providing a conductive layer over at least a portion of the dielectric layer, wherein the dielectric layer is disposed between the semiconductor layer and the conductive layer; defining a gate region from the conductive layer, a channel region being in the semiconductor layer and defined by the gate region; and before depositing the dielectric layer, defining a source region and a drain region in the semiconductor layer, the channel region being disposed between the source region and the drain region.

14. The method of claim 13 wherein the dielectric layer further comprises at least one of oxygen, silicon, or nitrogen.

15. The method of claim 13 wherein the semiconductor layer is provided over a substrate, and the substrate comprises silicon.

16. The method of claim 13, wherein the cleaning and passivating comprises using (NH.sub.4).sub.2S for sulfur passivation.

17. The method of claim 13, wherein the cleaning and passivation comprises: removing a native oxide; performing a native oxide cleaning; and passivating the semiconductor layer using at least one of (NH.sub.4).sub.2S or NH.sub.4OH.

18. The method of claim 13, wherein the cleaning and passivation consists essentially of gas-phase processing.

19. The method of claim 13, wherein the cleaning and passivation consists essentially of liquid-phase processing.

20. A method comprising: providing an InP layer on a substrate; forming a source region and a drain region in the InP layer, a channel region being disposed in the InP layer and between the source region and the drain region; after forming the source region and the drain region, removing a native oxide on the InP layer using a HF-based gas, a HCl-based gas, or a combination thereof in a chamber; performing a cleaning process and OH-passivating the InP layer after removing the native oxide, the cleaning process and the OH-passivating using a NH.sub.4OH gas in situ in the chamber; S-passivating the InP layer after performing the cleaning process and OH-passivating, the S-passivating the InP layer using a (NH.sub.4).sub.2S gas in situ in the chamber; after the S-passivating the InP layer, depositing by ALD a high-k dielectric layer on the InP layer; and forming a gate electrode on the high-k dielectric layer, wherein the high-k dielectric layer is disposed between the InP layer and the gate electrode, the channel region being defined by the gate electrode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1(a)-(b) are schematic cross-sectional views illustrating an embodiment of the invention including the implantation and anneal of source and drain regions through a layer that is subsequently removed;

(2) FIGS. 2(a)-(j) are schematic cross-sectional views of enhancement-mode InP MOSFETs fabricate in accordance with embodiments of the invention, and charts describing experimental procedures and data obtained for enhancement-mode InP MOSFETs;

(3) FIGS. 3(a)-(d) are schematic cross-sectional views illustrating the fabrication of InP-based devices on lattice-mismatched substrates such as silicon, in accordance with an embodiment of the invention;

(4) FIGS. 4(a)-(c) are schematic cross sectional views illustrating fabrication of an enhancement-type InP MOSFET, in accordance with an embodiment of the invention;

(5) FIGS. 5(a)-(g) are schematic cross-sectional views illustrating a method of making a self-aligned gate structure for an InP-based MOSFET, according to an embodiment of the invention;

(6) FIGS. 6(a)-(b) are schematic cross-sectional views illustrating dielectric layers deposited on an InP substrate; and

(7) FIGS. 7(a)-(d) are schematic cross sectional views illustrating a method of implantation and amorphization of source and drain regions through a diffusion/barrier layer and subsequent recrystallization of the source and drain regions and oxidation to improve the layer's dielectric properties.

DETAILED DESCRIPTION

(8) Aspects of this invention address, among other things, the challenges of forming a high-quality interface between a gate dielectric and InP and other InP-based materials through the use of ALD. See also Y. Q. Wu, et al., “Inversion-type enhancement-mode InP MOSFETs with ALD Al.sub.2O.sub.3, HfO.sub.2 and HfAlO nanolaminates as high-k gate dielectrics,” Proceedings of 65.sup.th Device Research Conference, Notre Dame, USA (2007) and Y. Q. Wu, et al., “Enhancement-mode InP n-channel metal-oxide-semiconductor field-effect-transistors with atomic-layer-deposited Al.sub.2O.sub.3 dielectrics,” Applied Physics Letters 91, 022108-022110 (2007), incorporated by reference herein in their entireties.

(9) Referring to FIG. 1(a), a semiconductor substrate 100 has an InP-based top layer 110 disposed thereover. In various embodiments, a portion of this InP layer may be used to form a channel for a transistor. The substrate 100 may include a semiconductor material and may be, for example, a bulk silicon wafer, a bulk germanium wafer, a semiconductor-on-insulator (SOI) substrate, or a strained semiconductor-on-insulator (SSOI) substrate. The substrate 100 may include or consist essentially of a first semiconductor material, such as a group IV element, e.g., germanium or silicon. In an embodiment, the substrate 100 includes or consists essentially of (100) silicon. In some embodiments, the substrate 100 is an InP substrate, with a top region of the InP substrate defining the InP-based top layer 110.

(10) The InP-based top layer 110 may be formed by molecular beam epitaxy (MBE), a chemical vapor deposition (CVD) process, e.g., metalorganic CVD (MOCVD), or other deposition techniques on the substrate 100. In an embodiment in which the InP-based top layer 110 is InP disposed over an InP substrate, the top layer may have a thickness ranging from, e.g., 1 nm to 100 μm. In an embodiment, the composition and lattice constant of the InP-based top layer 110 is different from the composition and lattice constant of the substrate 100. In a preferred embodiment, the thickness of the InP-based top layer 110 is below its critical thickness and the InP-based top layer 110, i.e., the channel layer, may include a strained region. For example, with a lattice-mismatch of 5%, the critical thickness is about 15 nm, and the InP-based top layer 110 preferably has a thickness less than 15 nm. In other embodiments, the thickness of the InP-based top layer 110 is greater than the critical thickness and the layer is at least partially relaxed. In an embodiment, the InP-based top layer 110 is relaxed.

(11) In alternative embodiments, one or more layers of materials that are substantially lattice-matched to InP, such as InAlAs or InGaAs, or thin layers of non-lattice-matched III-V compounds, such as GaAs, InSb or InAs, are provided above the InP-based top layer 110 for use in forming transistor source, drain, and/or channel regions. Such thin layers of non-lattice-matched III-V compounds may be strained, which may result in enhanced performance characteristics such as improved electron and/or hole mobility. As used herein, “substantially lattice-matched to InP” means having a lattice constant difference with a lattice constant of InP of no greater than about 10%, preferably no greater than about 5% . To maintain strain in non-lattice-matched III-V compounds, such as GaAs, InSb, and InAs, the thickness of such layers is preferably less than about 10 nm.

(12) As used herein, the term “InP-based materials” is used to refer to compositions that include or consist essentially of InP and may include additional elements. As used herein, “InP-based material layer structure” is used to refer to an InP layer or InP-based layer alone or in combination with one or more layers that are substantially lattice matched to InP or in combination with thin, strained, non-lattice-matched III-V layers.

(13) To prevent damage to the top layer during ion implantation, such as when creating transistor source and drain regions, an encapsulation protection layer 120, i.e., a dielectric layer, is disposed on the top surface of the InP-based top layer 110. This protection layer allows implantation therethrough while preventing damage of the InP-based top layer. Examples of a suitable protection layer include a SiO.sub.2 or SiN layer deposited by a CVD process, e.g., MOCVD, or an Al.sub.2O.sub.3 layer or a nanolaminate layer, including a material such as HfO.sub.2 and/or HfAlO, deposited by ALD. A mask 130 is formed above the protection layer, and used to define a gate region 140, a source region 150 and a drain region 160 for a transistor. The mask forms a dummy gate structure 170, which serves as a hard mask for a subsequent ion implantation step. The mask may be formed from a suitable masking material, such as a dielectric material, e.g., Si.sub.3N.sub.4, in accordance with methods known to one of skill in the art.

(14) The source and drain regions 150, 160 are defined in the InP-based top layer by performing an appropriate source/drain dopant ion implantation 180, using conventional techniques known to those of skill in the art, taking into account the composition of the protection layer. A channel region 190 is provided between the source and drain regions and includes at least a portion of the InP-based top layer 110, i.e., the channel layer. An anneal is then performed at a suitably high temperature to activate the implanted dopant, for example between about 600 and 900° C. with rapid thermal processing (“RTP”). The encapsulation protection layer protects the InP-based material surface during the implantation and anneal processes.

(15) The encapsulation protection layer and the dummy gate structure may be removed after the implantation and anneal steps to create a device-ready InP-based top layer 110 as shown in FIG. 1(b). Optionally, to improve the surface quality of the InP-based top layer prior to device fabrication, a portion of its top surface may be removed to ensure the elimination of any portion that is or may be damaged. Another optional method to improve the quality of the InP-based top layer 110 is to provide an additional protective/sacrificial cap layer (not shown) on the top surface InP-based top layer 110 before forming the protection layer 120, for example, a passivation layer including one or more materials such as S, NH.sub.4OH, amorphous Si, and/or amorphous Ge.

(16) Subsequently, the surface of the InP-based top layer 110 is cleaned, and a high-quality gate dielectric layer (not shown) is deposited by, e.g., an ALD process in, for example, an ASC F-120 ALD reactor. The gate dielectric layer may be a high-k dielectric. Exemplary gate dielectric structures include, for example, a layer of Al.sub.2O.sub.3, a layer of HfO.sub.2 layer, a nanolaminate layer of HfO.sub.2 and Al.sub.2O.sub.3, or HfAlO, or any other suitable gate dielectric material. A post-deposition anneal (PDA) may be performed using O.sub.2, N.sub.2 or any other suitable ambient at an appropriate temperature, for example between about 400 and 700° C.

(17) A gate (not shown) is formed above the channel region. At least a portion of the gate dielectric is disposed between the gate and the channel region, and the transistor operates as an inversion-type enhancement-mode device, i.e., a device that is off at a gate voltage V.sub.g=0, and is on at V.sub.g>0.

(18) As is known to those skilled in the art, there has been a long-time standing Fermi-level pinning issue in fabricating III-V compound semiconductor MOSFET devices. As discussed in the context of FIG. 2, this issue is addressed in embodiments of the instant invention.

(19) FIGS. 2(a)-(b) illustrate examples of InP MOSFETs. An InP MOSFET 200 may be formed as follows. First, an appropriately doped or semi-insulating semiconductor substrate with an InP-based channel layer is provided, i.e., an InP-based layer 110, over a substrate 100. Optionally, an additional epitaxial layer 200 may be deposited above the InP channel layer as described above for FIG. 1., e.g., by CVD, MOCVD or MBE. This additional epitaxial layer 200 may be InP and may include multiple layers of a material other than InP, such as InSb, InAs, GaAs, InAlAs, and/or InGaAs that may be substantially lattice-mismatched to InP. In order to maintain strain in the epitaxial layer 200, its thickness may be below the critical thickness.

(20) An appropriate source and drain ion implantation is performed to create source and drain regions 150, 160 that have a conduction type opposite to that of the channel region, i.e., with n-type source and drain for a p-type channel (for an n-type inversion-type MOSFET), or with p-type source and drain for an n-type channel (for a p-type inversion-type MOSFET). For example, an appropriate p-type source and drain implantation may be a Group II element such as Mg, Be, etc., with a dosage ranging from, e.g., 4×10.sup.17/cm.sup.3 to 1×10.sup.19/cm.sup.3, with an implantation depth of, e.g., 1 nm to 1 μm. An appropriate n-type source and drain implantation may be a Group IV element, e.g., Si, Ge, etc. with a dosage ranging from, e.g., 4×10.sup.17/cm.sup.3 to 1×10.sup.19/cm.sup.3 with an implantation depth of, e.g., 1 nm to 1 μm. A target for both n-type and p-type source and drain implantations is to achieve dosage levels as high as are typically attained in Si devices. This may be a challenge in InP-based materials because n-type dopants in a III-V material may exhibit p-type behavior above a certain concentration. For example, n-type dopant Si, when present in a concentration greater than about 1×10.sup.19/cm.sup.3 in InP, exhibits p-type behavior. A high-quality gate dielectric 210 is formed, typically by first performing a surface-preparation step including a liquid-phase pretreatment or a gas-phase pretreatment employing, e.g., (NH.sub.4).sub.2S or (NH.sub.4)OH, followed by surface treatment with hydrogen or nitrogen plasma, either in-situ in the same chamber, if feasible, or ex-situ. Preferably an ALD process is used to deposit a high-k dielectric layer. The gate dielectric layer may be an Al.sub.2O.sub.3 layer, an HfO.sub.2 layer, a nanolaminate layer of HfO.sub.2 and HfAlO, a group-II oxide, or any other dielectric material such as a rare-earth oxide or metallic oxide. The gate dielectric layer may have a thickness selected from a range of 1 nm to 1000 nm, preferably 1 nm-10 nm. The gate 220 is defined by conventional gate electrode deposition and lithographic patterning. Subsequently, source and drain ohmic contacts are formed.

(21) FIG. 2(b) illustrates the structure of a prototype inversion-type InP MOSFET 230, integrated with a high-k dielectric deposited by ALD. The substrate 100 may be an InP semi-insulating substrate. The source and drain regions 150, 160 are defined over an Si implanted n+ region 240. The gate dielectric 210 may be formed from a high-k dielectric, such as Al.sub.2O.sub.3, HfO.sub.2, or HfAlO, and/or combinations thereof. The gate 220 is formed from a suitable conducting material, such as nickel/gold.

(22) The InP MOSFET 230 operates as an inversion-type, enhancement mode device. Because the source and drain regions are of a doping type opposite to that of the channel, e.g., n-type source and drain regions and a p-type channel, at a gate voltage V.sub.g=0, the device is off, such that no current flows between the source and drain.

(23) FIG. 2(c) summarizes the key steps for the fabrication of Al.sub.2O.sub.3/InP MOSFETs by use of ALD on an InP semi-insulating substrate, as illustrated in FIG. 2(b). Prior to the formation of the high-k gate dielectric 210, surface cleaning and preparation of the substrate 100 includes HF- or HCl-based native oxide removal, NH.sub.4OH-based native oxide cleaning and OH-group passivation, and (NH.sub.4).sub.2S based sulfur passivation. These ex-situ wet-cleaning process steps may be extended to an in-situ gap-phase dry-cleaning process that comprises HF or HCl gas-phase cleaning, NH.sub.4OH gas-phase cleaning, and (NH.sub.4).sub.2S gas-phase passivation. Additionally, acetone, methanol, and iso-proponal cleaning may be performed.

(24) After surface degreasing and (NH.sub.4).sub.2S-based pretreatment, the substrate is transferred in a room ambient to an ALD reactor, such as an ASM F-120 ALD reactor, for gate dielectric 210 formation. The gate dielectric 210 may be, for example, an Al.sub.2O.sub.3 layer having a thickness of, e.g., 30 nm, deposited at a substrate temperature of 300° C., using alternately pulsed chemical precursors of Al(CH.sub.3).sub.3 (the Al precursor) and H.sub.2O (the oxygen precursor) in a carrier N.sub.2 gas flow.

(25) Source and drain regions 150, 160 are selectively implanted through the 30 nm thick Al.sub.2O.sub.3 layer, e.g., with a Si dose of 1×10.sup.14 cm.sup.−2 at 140 keV. Implantation activation may be achieved by rapid thermal anneal (RTA), e.g., at 720° C. for 10 seconds. Regrown oxide may be etched away using BHF. A thin layer of Al.sub.2O.sub.3 or HfO.sub.2 or HfAlO (e.g., 8 nm) is deposited, and a post deposition anneal is performed. Those of skill in the art are familiar with suitable alternative materials and process parameters for surface preparation and implantation and activation of source and drain regions.

(26) The source and drain ohmic contacts may be defined by an electron beam evaporation of a combination of AuGe/Pt/Au and a lift-off process, followed by a RTA process at 500° C. for 30 seconds, also in an N.sub.2 ambient.

(27) The gate electrode may be defined by electron beam evaporation of conductive materials, such as Ni/Au, Ti/Au, AuGe/Ni/Au, and/or AuGe/Pt/Au and a lift-off process.

(28) Referring now to FIGS. 2(d)-(j), data for an enhancement-mode n-channel InP MOSFET fabricated on a semi-insulating substrate with (ALD) Al.sub.2O.sub.3 as the gate dielectric are shown. The results illustrated in FIGS. 2(d)-(j) are for MOSFETs with nominal gate lengths varying from 0.75 μm to 40 μm and a gate width of 100 μm. Transfer-length-method (TLM) structures are used to determine contact resistance of 2.5 ohm-mllimeter (Ω.Math.mm) and sheet resistance of 230 Ω/sq. at the implanted area. Measurements are made with standard equipment such as an HP4284 LCR meter for the capacitance measurement and a Keithley 4200 for measurement of the MOSFET output characteristics.

(29) FIG. 2(d) illustrates the drain current vs. drain bias as a function of gate bias for a 1 μm InP MOSFET with 8 nm regrown Al.sub.2O.sub.3 as gate dielectric. In particular, the figure illustrates the dc I.sub.ds−V.sub.ds characteristic with a gate bias from 0 to 8 V. The measured MOSFET has a designed gate length at mask level (LMask) of 0.75 μm and a gate width (L.sub.w) of 100 μm. A maximum drain current of 70 mA/mm is obtained at a gate bias of 8 V and a drain bias of 3 V. The gate leakage current is below 10 μA/mm under the same bias condition, more than 4 orders of magnitude smaller than the drain on-current. A maximum transconductance g.sub.m is approximately 10 millisiemens/mm (mS/mm) and an output conductance of approximately 3 mS/mm (V.sub.g=8 V). The relatively low g.sub.m may be improved by reducing the thickness of the dielectric, increasing the dielectric constant, and improving the quality of the interface.

(30) Since the fabrication process used in some embodiments is not self-aligned, accurate determination of the effective gate length and series resistance is especially important for evaluating the intrinsic device performance and the potential for further optimization. FIG. 2(e) illustrates measured channel resistance vs. mask gate length for different gate biases with Al.sub.2O.sub.3 thickness of 30 nm. Specifically, FIG. 2(e) shows the effective gate length (L.sub.eff) and series resistance (R.sub.SD) extracted by plotting channel resistance R.sub.Ch vs. L.sub.Mask. R.sub.SD and ΔL, which is the difference between L.sub.Mask and L.sub.eff, are determined to be 38.6 Ω.Math.mm and 0.5 μm, respectively, by the equation below:

(31) $\begin{array}{cc}\frac{V_{\mathrm{ds}}}{I_d}=R_{\mathrm{Ch}}=\frac{L_{\mathrm{eff}}}{W{\mu }_{\mathrm{eff}}{C}_G\left(V_{\mathrm{GS}}-V_T\right)}=\frac{L_{\mathrm{Mask}}-\Delta L}{W{\mu }_{\mathrm{eff}}{C}_G\left(V_{\mathrm{GS}}-V_T\right)}& \left(1\right)\end{array}$
The effective electron mobility μ.sub.eff is weakly dependent on gate bias from 2-4 V and is taken as a constant in this calculation. R.sub.SD and L.sub.eff is determined as the intercept of the linear fitting of R.sub.Ch at different gate biases and L.sub.mask as shown in FIG. 2(e). The R.sub.SD value of 386Ω and the ΔL value of 0.5 μm were determined using line fitting. The obtained R.sub.SD is consistent with the results from measurement by a TLM technique since R.sub.SD includes contact resistance, sheet resistance, accumulation resistance and spread resistance. ΔL is caused by the inter-diffusion of source and drain implant activation and the proximity effect of the photolithography process.

(32) FIG. 2(f) illustrates extrinsic and intrinsic drain current and trans-conductance vs. gate bias. In particular, to evaluate the output characteristics more accurately, the intrinsic transfer characteristics is calculated by subtracting the series resistance R.sub.SD and using effective gate length L.sub.eff instead of mask gate length L.sub.Mask and compared with the extrinsic one, as shown in FIG. 2(f). The intrinsic drain current and transconductance are only about 10% larger than the extrinsic ones due to the large gate length of 20 μm. FIG. 2(f) also shows that the subthreshold characteristic is scarcely changed. However, the threshold voltage determined by conventional method of linear region extrapolation does show some difference as highlighted as extrinsic threshold voltage V.sub.T and intrinsic threshold voltage V.sub.T* in FIG. 2(b).

(33) To better extract the threshold voltage, which is an important parameter in E-mode device characterization, several different methods are used to determine V.sub.T* on various gate lengths as presented in FIG. 2(g). FIG. 2(g) illustrates threshold voltage vs. the gate length using the intrinsic I-V characteristics of the device using five different methods—the ratio method (RM), the extrapolation in the linear region method (ELR), the second derivative method (SD), the second derivative logarithmic method (SDL), and the match-point method (MP). The figure shows that the linear method may not be appropriate for determine threshold voltage for a non-self-aligned process. The second derivative method and ratio method give mostly the same value at the long gate length device and both show V.sub.T* roll-off behavior for the submicron gate length device. These two methods may be more reliable ways to determine threshold voltage since the conducting mechanism changes during the transition near threshold, when drain current increases from exponentially to linear or quadratic dependence on the effective gate voltage (V.sub.g-V.sub.T).

(34) FIG. 2(h) illustrates drain current vs. drain bias as a function of gate bias for a 2 μm InP MOSFET with 8 nm Al.sub.2O.sub.3 gate oxide. In particular, the sub-threshold slope (S.S>) and DIBL characteristics of 280 mV/dec and 50 mV for the MOSFET are illustrated.

(35) FIG. 2(i) illustrates effective mobility vs. normal electric field for the InP MOSFET with 30 nm Al.sub.2O.sub.3 gate oxide and a 100 kHz split-CV measurement. Effective mobility is another important parameter for evaluating MOSFET performance. The “Split-CV” method is used to measure the channel capacitance, which may be used to calculate the total inversion charge in the channel by integrating the C-V curve. The inset of FIG. 2(i) is a 100 kHz C-V curve between gate and channel measured on a 40 μm gate length device from which inversion capacitance is seen clearly. The extracted mobility has a peak value of 650 cm.sup.2/Vs around a normal electric field of 0.22 MV/cm as shown in FIG. 2(i). Better mobility performance may be achievable by using an epitaxial InP layer to improve host material quality and optimize the device fabrication process.

(36) Detailed C-V measurements of MOS capacitors were carried out to evaluate the interface quality of Al.sub.2O.sub.3 formed by ALD on InP. FIG. 2(j) illustrates C-V measurements of an 8 nm Al.sub.2O.sub.3/n-InP MOSCAP from quasi-static up to 1 MHz.

(37) Specifically, the samples include 8 nm thick Al.sub.2O.sub.3 deposited on an n-type InP substrate at 300° C. by ALD. A 500° C. post deposition annealing improves C-V characteristics only moderately for InP as shown in FIG. 2(j), in contrast to the GaAs case. The frequency dispersion at accumulation capacitance may be attributed to the relative high interface trap density (D.sub.it) at the conduction band edge, though the extrinsic parasitic effects could also contribute to the frequency dispersion partly. The mid-gap D.sub.it is estimated to be approximately 2-3×10.sup.12/cm.sup.2−eV determined by the high-frequency (HF)-low-frequency (LF) method. This value is consistent with the value determined from the m-factor, a parameter related to sub-threshold characteristics. More specifically, the subthreshold slope is relatively large due to the large gate oxide thickness or the small oxide capacitance C.sub.ox and the existing interface trap capacitance C.sub.it. M-factor is defined as 60 mV/dec.×(1+C.sub.it/C.sub.ox). From the measured sub-threshold slope, an interface trap density D.sub.it of ˜2-3×10.sup.12/cm.sup.2−eV is determined.

(38) Moderate hysteresis of 100-300 mV exhibits in the C-V loops (not shown). The C-V characteristics in FIG. 2(j) show a clear transition from accumulation to depletion for HF C-V and the inversion features for LF C-V and quasi-static C-V indicating that the conventional Fermi-level pinning phenomenon reported in the literature is overcome in this ALD Al.sub.2O.sub.3/InP sample. The unpinning of the Fermi level may be attributed to the self-cleaning ALD Al.sub.2O.sub.3 process that removes the native oxide on the InP surface, similarly to the situation in ALD Al.sub.2O.sub.3 formed on GaAs. The unpinning of the Fermi level by the ALD Al.sub.2O.sub.3 process described above is significant, as it contributes to the realization of enhancement-mode MOSFETs on InP, as demonstrated in FIG. 2(d).

(39) The ALD process on III-V compound semiconductors enables the formation of high-quality gate dielectrics and unpinning of the Fermi level on compound semiconductors. A 0.75-μm gate-length E-mode n-channel MOSFET with an Al.sub.2O.sub.3 gate oxide thickness of 30 nm may have a gate leakage current less than 10 μA/mm at a gate bias of 8 V, a maximum drain current of 70 mA/mm, and a transconductance of 10 mS/mm. The peak effective mobility is ˜650 cm.sup.2/Vs and the interface trap density of Al.sub.2O.sub.3/InP is estimated to be ˜2-3×10.sup.12/cm.sup.2 eV.

(40) The prototype measurements reflected in FIGS. 2(d)-(j) reflect the use of Al.sub.2O.sub.3 as the gate dielectric. Alternatively other materials, such as Hf-based high-k materials, can be used for the gate dielectric. An exemplary process for formation of HfO.sub.2 as a dielectric by using ALD is to use ALD precursors such as HfCl.sub.4, TEMAHf or TDMAHf and oxygen precursors such as H.sub.2O or O.sub.3. A typical HfO.sub.2 ALD process is performed between 200-350° C. Surface cleaning and preparation is similar with use of materials such as HF, HCl, NH.sub.4OH and (NH.sub.4).sub.2S.

(41) For InP devices, such as the examples of FIGS. 2(a)-(j), the substrate may be a semi-insulating InP substrate or alternatively may be another material that supports an InP channel device. For example, a Si or SOI substrate, can provide cost and manufacturing advantages because of the possibility of using large-scale wafers and the well-developed Si-based processing facilities.

(42) InP-based devices may be integrated on Si substrates by the use of aspect ratio trapping (ART) techniques. Two exemplary approaches for such integration using ART techniques are illustrated in FIGS. 3(a)-(d). A detailed description of ART techniques may be found in U.S. patent application Ser. No. 11/728,032, incorporated herein in its entirety.

(43) FIGS. 3(a)-3(b) show how ART techniques may be used to grow a high-quality InP layer above a buffer layer on a lattice-mismatched underlying material, such as a Si wafer. The crystalline substrate may have a lattice constant substantially different from a lattice consant of InP. As illustrated in FIG. 3(a), a non-crystalline material, e.g., a dielectric layer 300, is formed over the substrate 100. The dielectric layer 300 may include a dielectric material, such as silicon nitride or silicon dioxide. The dielectric layer 300 may be formed by a method known to one of skill in the art, e.g., thermal oxidation or plasma-enhanced chemical vapor deposition. As illustrated, the dielectric layer 300 has a thickness t.sub.1 corresponding to a desired height of crystalline material to be deposited in a window 310 formed through the dielectric layer 300. In some embodiments, the thickness t.sub.1 of the dielectric layer 300 is selected from a range of, e.g., 20-50000 nm.

(44) A mask (not shown), such as a photoresist mask, is formed over the substrate 100 and the dielectric layer 300. The mask is patterned to expose at least a portion of the dielectric layer 300. The exposed portion of the dielectric layer 300 is removed by, e.g., reactive ion etching (RIE) to define the window 310 in the non-crystalline mask, i.e., in the dielectric layer 300. The window 310 extends to a surface of the substrate 100 and may be defined by at least one sidewall 320. The sidewall 320 is formed from the dielectric layer 300 and is, therefore, non-crystalline. The sidewall 320 may have a height h at least equal to a predetermined distance H from the surface of the substrate 100, i.e., the sidewall extends above the substrate by the height h. It has been observed experimentally that dislocations in a mismatched cubic semiconductor grown on a Si (100) surface in the near-vicinity (e.g., within approximately 500 nm or less) of a vertical dielectric sidewall 420 surface bend toward that surface at approximately 30 degrees through 60 degrees. For example, the dislocations may bend toward that surface at approximately a 45 degree angle to that surface. Based on this relationship, one may typically expect the predetermined distance H necessary to trap defects to be approximately equal to a width between ½w and 2w, where w is the width of the window.

(45) The window 310 may be substantially rectangular in terms of cross-sectional profile, a top view, or both, and have a width w that is smaller than a length l (not shown) of the window. For example, the width w of the window may be less than about 5000 nm, e.g., about 20-1000 nm. In some embodiments, the width of the window is about 150 nm. A length l of the window may exceed each of w and H. The ratio of the height h of the window to the width w of the window may be ≧1, and preferably is between about 1 and about 50.

(46) A crystalline buffer layer 330 including a material, such as Ge or InP, that has a lattice mismatch with the substrate 100 material, e.g., Si, is epitaxially grown within the opening 310. By configuring the aspect ratio of the height of the mask relative to the width of the opening, defects arising from deposition of the buffer layer may exit at the sidewalls below the top surface of the mask layer. This provides a high-quality top surface of the buffer layer 330 upon which the InP-based top layer 110 may be grown epitaxially.

(47) In particular, the buffer layer 330 may include a second crystalline semiconductor material that may include or consist essentially of a group IV element or compound, a III-V compound, and/or a II-VI compound. Examples of suitable group IV elements or compounds include germanium, silicon germanium, and silicon carbide. Examples of suitable III-V compounds include gallium arsenide, gallium nitride, indium arsenide, indium antimonide, indium aluminum antimonide, indium aluminum arsenide, indium phosphide, and indium gallium arsenide. Examples of suitable II-VI compounds include zinc selenide and zinc oxide. The buffer layer 330 is lattice-matched to the InP-based top layer 110 formed thereover, i.e., the buffer layer 330 may have a second lattice constant substantially similar to the lattice constant of InP.

(48) The second crystalline semiconductor material may be formed by selective epitaxial growth in any suitable epitaxial deposition system, including, but not limited to, MOCVD, atmospheric-pressure CVD (APCVD), low- (or reduced-) pressure CVD (LPCVD), ultra-high-vacuum CVD (UHCVD), MBE, or ALD. In the CVD process, selective epitaxial growth typically includes introducing a source gas into the chamber. The source gas may include at least one precursor gas and a carrier gas, such as, for example, hydrogen. The reactor chamber may be heated by, for example, RF-heating. The growth temperature in the chamber may range from about 300° C. to about 900° C., depending on the composition of the epitaxial region. The growth system may also utilize low-energy plasma to enhance the layer growth kinetics. CVD has a number of advantages, including the capability for depositing films with low defect densities and rapidly varying alloy compositions, as well as high quality regrowth capability. CVD may also provide improved manufacturability due to relatively higher throughput, relatively short downtimes, and scalability to very large reactors.

(49) The epitaxial growth system may be a single-wafer reactor or a multiple-wafer batch reactor. Suitable CVD systems commonly used for volume epitaxy in manufacturing applications include, for example, an Aixtron 2600 multi-wafer system available from Aixtron, based in Aachen, Germany; an EPI CENTURA single-wafer multi-chamber systems available from Applied Materials of Santa Clara, Calif.; or EPSILON single-wafer epitaxial reactors available from ASM International based in Bilthoven, The Netherlands.

(50) Dislocation defects in the second crystalline semiconductor material reach and terminate at the sidewalls 320 of the window in the dielectric material 300 at or below a vertical predetermined distance H from the surface of the substrate, such that dislocations in the second crystalline semiconductor material decrease in density with increasing distance from the bottom portion of the window. Accordingly, the upper portion of the buffer layer 330 is substantially exhausted of dislocation defects. Various dislocation defects such as threading dislocations, stacking faults, twin boundaries, or anti-phase boundaries may thus be substantially eliminated from the upper portion of the epitaxial region. A density of such dislocation defects may be less than, for example, 10.sup.6/cm.sup.2, preferably less than 10.sup.3/cm.sup.2. The second crystalline semiconductor material may be either substantially relaxed or strained.

(51) The InP-based top layer 110, i.e., the channel layer, is formed over the buffer layer 330, the channel layer being substantially lattice-matched with the buffer layer. After using ART techniques to provide a high-quality InP-based top layer 110, the techniques as described above in connection with FIGS. 1 and 2 may be used to create a device 340, such as a transistor, which incorporates the InP-based top layer, preferably as a channel. The source and drain regions of the transistor may also be formed in the channel layer, and a gate formed above the channel layer.

(52) Although using a Si substrate provides cost and manufacturability advantages, ART techniques may be used with a variety of substrate and mask materials. As discussed in U.S. Ser. No. 11/728,032, the opening may be configured in a variety of ways based on materials and applications, such as in a trench configuration.

(53) Referring now to FIGS. 3(c)-(d), an alternative ART approach for providing an InP-based channel layer is described. The mask 300 defines a plurality of openings 310 above substrate 100. An InP-based material, such as InP, is epitaxially grown within the openings, which are configured with an aspect ratio so that the majority of defects arising from the lattice mismatch between the underlying substrate, e.g., Si and InP, exit the InP-based layer at the mask sidewalls within the openings. The InP-based material is epitaxially grown to extend above the mask 300 to define a high quality coalesced InP-based top layer 110, upon which InP-based devices 340, such as the MOSFETs described above with reference to FIGS. 1 and 2, may be fabricated.

(54) Creation and activation of the source and drain may be a challenging step in forming transistors such as an inversion-type InP MOSFET. An alternative to the implanted source/drain formation approach discussed above uses a replacement source/drain structure. Referring to FIG. 4(a), a semiconductor substrate 100 with an InP-based top channel layer 110 is provided, with predefined channel doping type and doping level. The channel may be, for example, p-type doped with a doping level of 1×10.sup.18/cm.sup.3 to 1×10.sup.19/cm.sup.3. For a III-V material such as InP, a suitable n-type dopant is a Group IV element, such as Si. A suitable p-type is a Group II element, such as Mg. A relatively high doping level is preferred for enabling the low contact resistances. It is a challenge, however, to dope InP and other III-V materials to a level greater than 1×10.sup.20/cm.sup.3.

(55) A gate dielectric 210 is deposited on the InP channel material according to the methods described above, for example using ALD to deposit a dielectric material such as Al.sub.2O.sub.3. The dielectric material may include hafnium, e.g, HfO.sub.2. Thereafter, a conductive layer, e.g., a gate electrode layer is formed over the gate dielectric, such that the dielectric layer is disposed between a semiconductor layer, i.e., the InP-based top channel layer 110, and the conductive layer. A gate 220 is defined in the conductive layer by patterning methods known to one of skill in the art.

(56) Using techniques known to those familiar with the art, a source region and a drain region are patterned in a lithographic mask next to the gate structure, and the portions of the InP-based top layer 110 in the source and drain regions are removed by, e.g., dry etching, to form source and drain recesses 400, 400′, as shown in FIG. 4(b). The source and drain recesses 400, 400′ are filled with an appropriate source/drain material 410 that has a doping type opposite to that of the channel region, as shown in FIG. 4(c). In an embodiment, InP may be grown epitaxially within the source and drain recesses 400, 400′ by CVD with doping performed in situ. With a p-type channel dopant, an n-type dopant may be used for the source and drain to create an n-MOSFET. The doping types are reversed for a p-MOSFET. Those of skill in the art understand how to use appropriate dopants and materials to achieve the desired device characteristics.

(57) This approach, including the regrowth of the source and drain in the recesses, may allow the achievement of higher doping concentrations in the source and drain regions, and may enable lower contact resistances. The MOSFET structure illustrated in FIG. 4c may be an inversion-type, enhancement-mode device. As discussed previously, at Vg=0, a pn-junction blockades the drain current in the channel so that the device is off. At Vg>0, the InP-based channel under the gate is inverted to become n-type, so the device is on with a large drain current.

(58) FIGS. 5(a)-(g) illustrate a method of creating a MOSFET with source and drain regions that are self-aligned to the gate, i.e., the edges of the source and drain regions next to the gate are defined by the same mask that defines the edges of the gate next to the source and drain regions. Referring to FIG. 5(a), a mask 500 defines the locations of the gate and channel locations over a substrate 100. The mask 500 functions as a dummy gate and also as a barrier to ion implantation in the channel region during creation of the source and drain regions 510, 520 by ion implantation, as shown in FIG. 5(b). The mask may be made from an appropriate material, such as photoresist. After ion implantation of the source and drain regions, an insulator 530 such as SiN is deposited over the mask 500 and source and drain regions 510, 520, and is then etched back to expose a top surface of the mask 500 (i.e., of the dummy gate) as shown in FIGS. 5(c)-5(d). Referring to FIG. 5(e), the dummy gate is then removed by a selective etch, e.g., by a wet etch such as KOH or TMAH, or a dry etch in a reactive ion etching system, to define an opening 540. A gate dielectric 550 and gate material layers 560 are deposited into the opening created by the removal of the dummy gate, and etched back as shown in FIGS. 5(f)-(g). Advantageously, this self-aligned gate procedure enables the use of InP as a channel material and ALD for depositing a high-k gate dielectric while maintaining small (sub-micron) feature sizes and spacing. Forming a dummy gate enables the formation of a self-aligned gate, without exposure of the device gate dielectric and gate electrode to a high temperature dopant activation process that may damage a high-k dielectric. The dummy gate approach includes forming a gate dielectric after a source/drain implantation and activation, rather than before these steps, as in a conventional process flow.

(59) InP is a binary compound semiconductor resulting from a relatively weak covalent bond between indium and phosphorous. While InP MOSFETs feature characteristics such as enhanced drain currents and improved performance with respect to Fermi-level pinning and higher electron saturation velocity, the relatively strong electropositivity of indium can be a disadvantage, resulting, for example, in the relatively high reactivity of InP with oxygen. Thus, for example, as shown in FIGS. 6(a)-6(b), to mitigate interfacial instability difficulties between InP and dielectric materials as well as to prevent incongruent sublimation of the III-V material InP, it is possible to use a diffusion/barrier layer 600 including a relatively inert materials such as transition metal nitrides or group III-nitrides (e.g., BN, AlN, MoN, TaN, TiN, or AlN, etc., which are much less reactive with InP than oxygen, especially at higher temperatures) adjacent the top surface of the InP-based top layer 110 of substrate 100. As shown in FIG. 6(b), the use of a relatively inert diffusion/barrier layer 600 permits the sequential deposition of a relatively non-inert dielectric 610 such as SiO.sub.2 or Al.sub.2O.sub.3 above the relatively inert layer. By use of ALD, the inert barrier layer 600 may be kept relatively thin, e.g., as thin as one monolayer (which typically will be about 15 angstroms (Å)), or preferably about 5 to 10 nanometers (nm), although the barrier layer can be substantially thicker, e.g., as thick as 1 μm or more. In alternative embodiments, the barrier layer may be AlN or AlON or a nanolaminate—e.g., alternating layers of AlN and Al.sub.2O.sub.3, deposited as monolayers or in layers of about 5 nm—which can enhance the ability of the barrier layer to trap materials such as In or P before they can diffuse through the barrier layer.

(60) FIGS. 7(a)-(d) illustrate a method of forming source and drain regions that also provides for an improved dielectric layer, e.g., an improved gate dielectric layer. In FIG. 7(a) a dielectric 700 inert to InP, such as a transition metal-nitride, is provided above an InP-based top layer 110 using ALD as described above for FIG. 6. In FIG. 7(b) the gate 710 is defined and the source and drain regions 720, 730 of a transistor are implanted using techniques similar to those discussed above for FIGS. 1 and 2, and the source and drain regions are amorphized. In an embodiment, amorphization is accomplished by using a heavy dopant species such as SiF.sub.x, with sufficient dopant dosage and energy to concomitantly accomplish both amorphization and high dopant concentration of the source/drain regions. In another embodiment, amorphization is accomplished by implanting an inert element such as argon or another suitable noble gas prior to the implantation of the dopant species. In still another embodiment, amorphization is accomplished by using a heavy dopant species such as SiF.sub.x, with sufficient dopant dosage and energy to concomitantly accomplish amorphization of and high dopant concentration in the source/drain regions. For example, complete amorphization of the InP lattice may be accomplished through the use of high dosage implants using compounds such as SiF.sub.x between 10.sup.14cm.sup.−2 and 10.sup.16cm.sup.−2 through dielectric layer(s). Easy displacement of the In sublattice along <0001> directions can enable amorphization through heavy dosage implantation.

(61) In FIG. 7(c) the source/drain regions 720, 730 are annealed at a temperature sufficiently high to ensure recrystallization, such as by RTA between 400° C. and 1000° C. Use of high implantation dosages and improved activation/ionization of the dopant species through recrystallization of the amorphized InP lattice lowers the contact resistance. Then in FIG. 7(d) an oxidizing species, e.g., PECVD SiO.sub.2, is introduced at a temperature of, e.g., 300° C., to enable formation of an oxynitride from the dielectric 700, e.g., from a dielectric transition metal nitride. Converting the dielectric transition metal nitride into an oxynitride provides an improved dielectric from the same layer that provided an effective diffusion barrier, eliminating the need to deposit new dielectric material. Effective performance of the transistor embodiment of FIG. 7 is enhanced by the use of ohmic contacts.

(62) In some embodiments, processes and materials analogous to the methods described above may be used to form a high electron mobility transistor (HEMT) including an InP-based material. A HEMT is a field effect transistor incorporating a junction between two materials with different band gaps (i.e., a heterojunction) as the channel instead of a doped region. An InP-based material may be incorporated in a HEMT as a portion of the channel layer.

(63) The embodiments disclosed above and their variations address a variety of challenges in providing enhanced MOSFET performance in a commercially viable way through various combinations of materials and techniques such as InP-based, ALD, and Al.sub.2O.sub.3 or Hf-based dielectrics in conjunction with various other features and steps. Those skilled in the art will understand how to substitute other materials and process steps to apply these inventive combinations to a variety of applications.