LOW NOISE AMPLIFIER

Abstract

A low noise amplifier comprising a first transconductance amplifier arranged to receive an input voltage at its input terminal and to generate an output current at its output terminal. A second transconductance amplifier is arranged such that its input terminal is connected to the input terminal of the first transconductance amplifier, and such that the output terminal of the second transconductance amplifier is connected to the input terminal of the second transconductance amplifier via a capacitive feedback network (C.sub.1).

Claims

1. A low noise amplifier comprising: a first transconductance amplifier having an input terminal and an output terminal, said first transconductance amplifier being arranged to receive an input voltage at its input terminal and to generate an output current at its output terminal; a second transconductance amplifier having an input terminal and an output terminal, said second transconductance amplifier being arranged such that: the input terminal of the second transconductance amplifier is connected to the input terminal of the first transconductance amplifier; and the output terminal of the second transconductance amplifier is connected to the input terminal of the second transconductance amplifier via a capacitive feedback network.

2. The low noise amplifier as claimed in claim 1, wherein the first transconductance amplifier is feedback-less.

3. The low noise amplifier as claimed in claim 1, wherein the first and second transconductance amplifiers and the capacitive feedback network are arranged on a chip, optionally wherein the chip comprises an RFIC.

4. The low noise amplifier as claimed in claim 1, wherein the capacitive feedback network comprises a first capacitor connected between the input and output terminals of the second transconductance amplifier, and a second capacitor connected between the output terminal of the second transconductance amplifier and a reference voltage.

5. The low noise amplifier as claimed in claim 4, wherein the reference voltage is ground.

6. The low noise amplifier as claimed in claim 4, wherein a ratio between the respective capacitance value of the first capacitor to a sum of the capacitance values of the first and second capacitors of the capacitive feedback network is constant.

7. The low noise amplifier as claimed in claim 4, wherein a respective capacitance value of the first capacitor and/or the second capacitor of the capacitive feedback network is configurable.

8. The low noise amplifier as claimed in claim 7, wherein the first capacitor and/or the second capacitor comprises a capacitor matrix.

9. The low noise amplifier as claimed in claim 4, wherein the capacitive feedback network comprises a third capacitor connected between the input terminal of the second transconductance amplifier and the reference voltage.

10. The low noise amplifier as claimed in claim 1, wherein the second transconductance amplifier comprises a current control circuit portion arranged to adjust a supply current drawn by said second transconductance amplifier.

11. The low noise amplifier as claimed in claim 1, wherein each transconductance amplifier comprises an inverter cell comprising a PMOS transistor and an NMOS transistor, arranged such that: a gate terminal of the PMOS transistor is connected to a gate terminal of the NMOS transistor at an inverter input terminal; a drain terminal of the PMOS transistor is connected to a drain terminal of the NMOS transistor at an inverter output terminal; a source terminal of the PMOS transistor is connected to a first rail; and a source terminal of the NMOS transistor is connected to a second rail.

12. The low noise amplifier as claimed in claim 11, wherein each of the gate terminals of the PMOS and NMOS transistors is connected to the inverter input terminal via respective DC blocking capacitor.

13. The low noise amplifier as claimed in claim 11, wherein the inverter cell of the first transconductance amplifier is arranged such that the inverter input terminal is connected to the input terminal of the first transconductance amplifier, and such that the inverter output terminal is connected to the output terminal of the first transconductance amplifier.

14. The low noise amplifier as claimed in claim 11, wherein the inverter cell of the second transconductance amplifier is arranged such that the inverter input terminal is connected to the input terminal of the second transconductance amplifier, and such that the inverter output terminal is connected to the output terminal of the second transconductance amplifier.

15. The low noise amplifier as claimed in claim 11, wherein a transconductance of the PMOS transistor is substantially equal to a transconductance of the NMOS transistor.

16. The low noise amplifier as claimed in any preceding claim 1, further comprising an external passive impedance transformation network.

17. The low noise amplifier as claimed in claim 16, wherein the external passive impedance transformation network comprises a capacitor and an inductor, arranged such that: a first terminal of the capacitor is connected to the wireless reception portion; a second terminal of the capacitor is connected to the input terminal of the first transconductance amplifier; a first terminal of the inductor is connected to the second terminal of the capacitor and to the input terminal of the first transconductance amplifier; and a second terminal of the inductor is connected to ground.

18. A radio receiver device comprising a low noise amplifier as claimed in claim 1, said radio receiver device further comprising a wireless reception portion arranged to receive a wireless communication signal over a wireless interface, and to generate an input voltage in response to said received communication signal, wherein the input voltage is provided to the input terminal of the first transconductance amplifier.

19. The radio receiver device as claimed in claim 18, further comprising a mixer, wherein the low noise amplifier is arranged to drive said mixer, optionally wherein said mixer comprises a current-mode passive mixer.

20. The radio receiver device as claimed in claim 19, further comprising a transimpedance amplifier, wherein the output of the mixer is connected to an input of the transimpedance amplifier.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0058] Certain embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:

[0059] FIG. 1 is a block diagram of a prior art multiband radio receiver;

[0060] FIG. 2 is a block diagram of a prior art filter-less multiband radio receiver;

[0061] FIG. 3A is a schematic diagram of an LNA in accordance with an embodiment of the present invention;

[0062] FIG. 3B is a schematic diagram showing an equivalent circuit to the topology of FIG. 3A;

[0063] FIG. 4 is a circuit diagram of a radio receiver device that uses the LNA of FIG. 3A;

[0064] FIGS. 5A and 5B are circuit diagrams of an LNA provided with an off-chip passive matching network;

[0065] FIG. 6 is a circuit diagram of a model used to calculate the noise contribution of the TIA op-amps used with the radio receiver device of FIG. 4;

[0066] FIGS. 7A and 7B are circuit diagrams of an LNA for a multiband receiver;

[0067] FIG. 8 is a circuit diagram of an LNA with a variable supply current in the second transconductance amplifier of the LNA;

[0068] FIG. 9A is a circuit diagram illustrating the biasing used in the second transconductance amplifier of the LNA;

[0069] FIG. 9B is a circuit diagram of a variable capacitor matrix for use in a multiband LNA;

[0070] FIG. 10 is a circuit diagram of an LNA having two different power modes;

[0071] FIG. 11 is a circuit diagram of a single-ended multiband LNA with programmable supply current employed in an on-chip inductor-less radio receiver with single-balanced passive current-mode IQ down conversion mixers;

[0072] FIG. 12 is a circuit diagram of a differential multiband LNA with programmable supply current employed in an on-chip inductor-less radio receiver with double-balanced passive current-mode IQ down conversion mixers; and

[0073] FIG. 13 is a circuit diagram of a CMOS inverter.

DETAILED DESCRIPTION

[0074] FIG. 1 is a block diagram of a prior art multiband radio receiver 2. In particular, this radio receiver 2 is implemented as a ‘direct conversion receiver’. The integrated direct conversion receiver 2 is shown with dashed lines and it is preceded by an off-chip, passive RF filter 4. In general, this RF ‘preselection’ filter 4 is needed to filter and attenuate harmful out-of-band blocking signals, which can drive the receiver 2 into compression.

[0075] Blocking signals may also desensitize the receiver 2 and lower the signal-to-noise-ratio (SNR) of the desired received RF signal received via the antenna 6. The integrated direct conversion receiver 2 is constructed from an LNA 8; in- and quadrature-phase (IQ) down conversion mixers 10, 12; a local oscillator (LO) circuit 14 that generates the down-converting IQ signals for the mixers 10, 12; an analogue baseband (ABB) circuits 16, 18 that include respective analogue baseband low-pass filtering and amplification; analogue-to-digital converters (ADC) 20, 22; and a digital circuit 24 for processing the output signals of ADCs 20, 22.

[0076] Today's wireless terminals and Internet-connected devices employ cellular—e.g. as 3G, 4G, or long term evolution (LTE)—chipsets with RF transceivers which need to support large number of frequency bands covering different areas and countries. As such, the radio receiver device 2 is a multiband wireless receiver, and thus includes multiple RF preselection filters 4a-c, and multiple LNAs 8a-c which are also needed in such an arrangement. In this particular example, the direct conversion receiver 2 of FIG. 1 can support reception at three different frequency bands, where each frequency band requires its own dedicated RF preselection filter 4a-c and associated LNAs 8a-c.

[0077] In some frequency-division multiplexing (FDD) radio systems, such as in 3G and 4G cellular systems, the receiver 2 and the transmitter (not shown) of the same RF transceiver simultaneously receive and transmit, i.e. the transceiver carries out full-duplex communication. In such an FDD RF transceiver, the RF preselection filter 4 is generally necessary in order to attenuate the large transmitted signal, which otherwise would leak to the input of the receiver 2 via a common receiver-transmitter antenna 6. In such cases, the receiver RF preselection filter 4 may also be realised as a duplexer filter, which also provides filtering to the transmitter. In practice, it is generally very difficult to omit the receiver RF preselection filter 4 in a full-duplex FDD system, since the level of the transmitted RF signal at the antenna 6 can be very large, e.g. +30 dBm.

[0078] However, in half-duplex RF transceivers, the receiver and transmitter do not operate simultaneously, and in such arrangements it may be possible to use a ‘filter-less’ receiver, such as the one shown in FIG. 2.

[0079] In a half-duplex system, the transmitter (not shown) and receiver 24 do not operate simultaneously and, as a result, the receiver 24 does not need to tolerate large RF signal transmitted by the colocated transmitter when receiving (potentially very weak) RF signals. For example, in half-duplex LTE radio systems for Internet-of-Things (IoT) applications, the receiver 24 generally needs to tolerate out-of-band signals of levels up to −15 dBm at the at the antenna port (i.e. the part of the receiver connected to the antenna 6) while providing sufficiently large SNR for the desired received signal. This blocking signal requirement is sufficiently relaxed that the integrated radio receiver 24 may have a sufficiently linear design so as to tolerate these out-of-band blockers without filtering them before they enter to the LNA. If this is the case, it may be possible to omit the RF preselection filters altogether.

[0080] In such an arrangement, it may be possible to provide only a single wideband or configurable LNA 26. In this context, configurable means that the LNA 26 can be configured to a desired operation frequency band. However, in practice, if the receiver needs to support wide band of frequencies, it may be necessary to employ more than one configurable LNA (not shown), for instance one LNA covering for low band (LB) frequencies, a second LNA supporting medium band (MB) frequencies, and a third LNA configurable to high band (HB) frequencies. The number of LNAs needed depends on the required operation frequency tuning range of the receiver. Nevertheless, as it is not uncommon for modern multiband receivers to need to support ten or more frequency bands in which a conventional multiband receiver would require ten separate RF preselection filters, ten LNAs, and ten LNA input pins on the RFIC, making use of e.g. three configurable LB, MB, and HB LNAs with no RF preselection filters may lead to much lower complexity and bills of material (BOM).

[0081] Such a multiband RF pre-selection filter-less receiver 24 generally requires an LNA architecture which needs to be wideband or configurable to a wide band of frequencies as outlined above. Typically, prior art integrated LNAs employ on-chip inductors, for example at their load, in order to tune out the parasitic capacitances and to cause the peak LNA gain to be at the frequency of interest. In a multiband LNA, a parallel inductor-capacitor (LC) resonance circuit at the LNA's load can be tuned to a wide band of frequencies, e.g. by using a capacitor matrix. In modern sub-micron complementary metal oxide semiconductor (CMOS) processes that use low supply voltages, the use of inductive loads at LNAs also allows for larger voltage headroom for blocking signals, which is especially important in RF preselection filter-less receivers in which there is no filtering for the blocking signals before they enter to the LNA, as outlined above.

[0082] Unfortunately, on-chip inductors require a significant amount of silicon area and scaling down the minimum transistor length in CMOS process scaling does not typically lead to a significant reduction in the silicon area required for such on-chip inductors. This means that the relative cost of on-chip inductors compared to any other components used in the RFIC increases with the CMOS process scaling in modern deep-submicron processes. On-chip inductors can potentially occupy the largest area in integrated LNAs. Due to the associated large silicon area requirement, on-chip inductors also pick up interference such as digital clock harmonics via magnetic coupling, which can be a serious issue in system-on-chips (SoCs) that usually contain large amount of digital circuitry. For these reasons, it is desirable to implement the LNA without on-chip inductors, i.e. as an on-chip inductor-less amplifier. Such an arrangement may also lower the cost of the RFIC.

[0083] The LNAs typically need to provide a stable input impedance (usually 50Ω for a single-ended LNA, or 100Ω for a differential LNA) for a proper termination impedance for the RF preselection filter or antenna in order to avoid issues. For example, if a RF preselection filter is not terminated with the correct impedance, the filter may exhibit an unacceptably high ripple at its passband and the filter transition band attenuation may be compromised. The LNAs need to also have low noise figure (NF) for high receiver sensitivity and they need to provide sufficiently large gain to suppress the noise of the circuits following the LNA. In modern radio receivers, the down conversion mixers are usually realized as current-mode passive mixers and in that case, it is convenient to define the LNA gain as equivalent transconductance (g.sub.m), which represents the RF voltage-to-current gain of the LNA. Finally, especially in RF preselection filter-less receivers, the LNAs typically need to have high linearity to tolerate out-of-band blocking signals.

[0084] To this end, conventional LNAs make use of RFB- or CFB-based topologies, known in the art per se, in which the transconductance amplifier of the LNA that provides the required gain is supplied with either resistive or capacitive feedback elements, i.e. feedback is provided in the signal path.

[0085] FIG. 3A is a schematic diagram of an LNA 28 in accordance with an embodiment of the present invention. FIG. 3B is a schematic diagram showing an equivalent circuit to the topology of the LNA 28.

[0086] In this arrangement, the LNA 28 is constructed from a pair of transconductance amplifiers 30, 32 arranged in parallel. The first transconductance amplifier 30 has a transconductance G.sub.mLNA and is arranged to provide the primary transconductance amplification of the LNA 28, i.e. it provides voltage-to-current gain. This particular transconductance amplifier 30 has no feedback loop.

[0087] In parallel with the first transconductance amplifier 30 is a second transconductance amplifier 32, which has a transconductance G.sub.mM. This second transconductance amplifier 32 has a capacitive feedback network constructed from first and second capacitors C.sub.1, C.sub.2. The first capacitor C.sub.1 is connected between the input and output terminals of the second transconductance amplifier 32, and the second capacitor C.sub.2 is connected between the output terminal of the second transconductance amplifier 32 and ground.

[0088] The second transconductance amplifier 32, which has the capacitive feedback network in its feedback path, provides input impedance matching for the LNA 28. This advantageously allows the first transconductance amplifier 30 to have large input and output impedances, while the second transconductance amplifier 32 sets the input impedance of the LNA 28 as a whole.

[0089] The proposed architecture can be used for both single-ended and differential LNA circuits.

[0090] As shown in FIG. 3B, the second transconductance amplifier 32, together with its capacitive feedback network C.sub.1, C.sub.2, can be seen as an equivalent resistance R.sub.EQ and capacitance C.sub.EQ connected to the input terminal of the first transconductance amplifier 30, i.e. they influence the effective input impedance of the LNA 28. The values of these equivalent resistance R.sub.EQ and capacitance C.sub.EQ are derived as per Equations 1 and 2 below respectively.

[00001]$\begin{array}{cc}\mathrm{Equivalent}\mathrm{resistance}{R}_{\mathrm{EQ}}& \\ R_{\mathrm{EQ}}=\frac{C_1+C_2}{C_1}\frac{1}{G_{\mathrm{mM}}}& \mathrm{Equation}1\\ \mathrm{Equivalent}\mathrm{capacitance}{C}_{\mathrm{EQ}}& \\ C_{\mathrm{EQ}}=\frac{C_1{C}_2}{C_1+C_2}& \mathrm{Equation}2\end{array}$

[0091] Here, R.sub.EQ is the input resistance of the LNA 28 and C.sub.EQ is the (undesired) input capacitance of the LNA 28. Assuming that at the frequency of interest (f.sub.0), that the angular frequency

[00002]${\omega }_0<<\frac{G_{mM}}{C_2},$

the input resistance matching requirement R.sub.IN of the LNA 28 is given as per Equation 3 below:

[00003]$\begin{array}{cc}\mathrm{Input}\mathrm{resistance}\mathrm{matching}\mathrm{requirement}\mathrm{of}\mathrm{the}\mathrm{LNA}28& \\ R_{\mathrm{IN}}=R_{\mathrm{EQ}}=R_S=\frac{C_1+C_2}{C_1}\frac{1}{G_{\mathrm{mM}}}& \mathrm{Equation}3\end{array}$

where R.sub.S is the source impedance.

[0092] In addition, at impedance match and also with

[00004]${\omega }_0<<\frac{G_{\mathrm{mM}}}{C_1},$

the voltage amplitude at the output of the second transconductance amplifier 32 (G.sub.mM) is given as per Equation 4 below:

[00005]$\begin{array}{cc}\mathrm{Voltage}\mathrm{amplitude}\mathrm{at}\mathrm{the}\mathrm{output}\mathrm{of}\mathrm{the}\mathrm{second}\mathrm{transconductance}\mathrm{amplifier}32& \\ v_{\mathrm{OUT},\mathrm{GmM}}\approx \frac{1}{{\omega }_0{C}_1{R}_S}{v}_{\mathrm{IN}}& \mathrm{Equation}4\end{array}$

where V.sub.IN is the voltage amplitude at the LNA input.

[0093] Importantly, no on-chip inductors are required in order to provide the input matching, i.e. the LNA 28 has no on-chip inductors. As can be seen in FIG. 4, when implemented within a radio receiver device 34, the LNA 28 may comprise an off-chip passive matching network 36. The input to the first transconductance amplifier 30 may be connected to the off-chip passive matching network 36, which may include any required inductors, as shown in FIG. 4.

[0094] A blocker signal presented at the input to the LNA 28 is also amplified to the output of the second transconductance amplifier 32 (G.sub.mM). However, the gain of the second transconductance amplifier 32 can be much lower than a conventional CFB or RFB LNA, in which the LNA may typically provide around 20 dB voltage gain. In the LNA architecture illustrated in FIG. 3A, the voltage gain in the parallel CFB amplifier may typically be in the order of only 10-13 dB. Accordingly, this means that the parallel CFB amplifier compresses at a much higher input blocker power compared to the traditional RFB or CFB LNA known in the art per se.

[0095] Additionally, because the CFB amplifier (i.e. second transconductance amplifier 32 and capacitive feedback network C.sub.1, C.sub.2) is in parallel with the signal path, its compression is much less concern compared to the conventional RFB or CFB LNAs, in which the compression takes place at the signal path.

[0096] The noise figure (NF) of the LNA 28 shown in FIG. 3A can be approximated as per Equation 5 below:

[00006]$\begin{array}{cc}\mathrm{Noise}\mathrm{figure}\mathrm{of}\mathrm{the}\mathrm{LNA}28& \\ \mathrm{NF}=1+\frac{\gamma }{G_{\mathrm{mM}}{R}_S}+\frac{4\gamma }{G_{\mathrm{mLNA}}{R}_S}=1+\frac{C_1}{C_1+C_2}\gamma +\frac{4\gamma }{G_{\mathrm{mLNA}}{R}_s}& \mathrm{Equation}5\end{array}$

in which it is assumed that R.sub.IN=R.sub.S. It is also assumed that both of the transconductance amplifiers 30, 32 are realised using similar CMOS inverters but potentially with different values of transconductance, FET dimensions, etc.

[0097] In Equation 5, the second and last terms are due to the second transconductance amplifier 32 (G.sub.mM) and first transconductance amplifier 30 (G.sub.mLNA) respectively.

[0098] Without the capacitive feedback network C.sub.1, C.sub.2 (i.e. if the input and output terminals of the second transconductance amplifier 32 were connected to the input terminal of the first transconductance amplifier 30), the NF due to the second transconductance amplifier 32 alone would be as per Equation 6 below:

NF=1+γ   Equation 6: Noise figure due to the second transconductance amplifier 32 alone without the capacitive feedback network

[0099] By comparing Equation 5 to the Equation 6, it can be seen that the noise due to the second transconductance amplifier 32 (G.sub.mM) is reduced by a factor C.sub.1/(C.sub.1+C.sub.2) via the capacitive feedback network C.sub.1, C.sub.2.

[0100] In some applications, however, the resulting NF of the complete LNA 28 shown in FIG. 3A may be too high, e.g. for some cellular applications. In order to overcome this, the NF of the proposed LNA 28 can be decreased further by designing the resistance R.sub.EQ to be larger than the source resistance R.sub.S and by employing a passive impedance transformation network 36 to transform R.sub.EQ downwards to R.sub.S. An example of this is shown in FIG. 4.

[0101] The ideally-lossless impedance matching network 36 amplifies the incoming RF voltage by a factor N, in which N.sup.2 is the resistance matching ratio of R.sub.EQ and R.sub.S as per Equation 7 below:

[00007]$\begin{array}{cc}\mathrm{The}\mathrm{resistance}\mathrm{matching}\mathrm{ratio}\mathrm{of}{R}_{\mathrm{EQ}}\mathrm{and}{R}_S& \\ N^2=\frac{R_{\mathrm{EQ}}}{R_S}& \mathrm{Equation}7\end{array}$

[0102] The impedance matching network 36 also tunes out the undesired capacitance of C.sub.EQ and all the other parasitic capacitance presented at the inputs of the transconductance amplifiers 30, 32. The NF of the complete LNA 28 with the passive impedance network 36 is then given as per Equation 8 below:

[00008]$\begin{array}{cc}\mathrm{Noise}\mathrm{figure}\mathrm{of}\mathrm{the}\mathrm{LNA}28\mathrm{together}\mathrm{with}\mathrm{the}\mathrm{off}\text{-}\mathrm{chip}\mathrm{impedance}\mathrm{matching}\mathrm{network}& \\ \mathrm{NF}=1+\frac{\gamma }{G_{\mathrm{mM}}{N}^2{R}_S}+\frac{4\gamma }{G_{\mathrm{mLNA}}{N}^2{R}_S}& \mathrm{Equation}8\end{array}$

[0103] It is seen that the noise contributions of the first and second transconductance amplifiers 30, 32 are reduced by a factor N.sup.2 compared to Equation 5.

[0104] The radio receiver device 34 of FIG. 4 is a direct conversion receiver. The first transconductance amplifier 30 (G.sub.mLNA) having ideally large input and output impedances drives the in-phase and quadrature mixers 38, 40, while the parallel CFB amplifier (i.e. the second transconductance amplifier 32 (G.sub.mM) with the capacitive feedback network C.sub.1, C.sub.2) provides the LNA input matching with the off-chip impedance matching network 36. Examples of the off-chip impedance matching network 36 are shown in FIGS. 5A and 5B.

[0105] The in-phase and quadrature mixers 38, 40 are connected to the output terminal of the first transconductance amplifier 30 via third capacitor C3, and are each provided with in-phase and quadrature reference signals generated by a local oscillator (LO) and divider 42. These mixers 38, 40 each drive a respective transimpedance amplifier 44, 46 that provides differential in-phase and quadrature output signals 48, 50 respectively. These transimpedance amplifiers 44, 46 have a topology known in the art per se and the structure and function of these is not described in detail here.

[0106] Thus the impedance matching network 36 amplifies the incoming RF voltage near the operation frequency by a factor of N, and it transforms the source resistance R.sub.S to a higher value of R.sub.EQ realised by the parallel CFB amplifier (i.e. the second transconductance amplifier 32 and capacitive feedback network C.sub.1, C.sub.2). The first transconductance amplifier 30 (G.sub.mLNA) drives the passive current mode mixers 38, 40, which in turn drive the TIAs 44, 46. The voltage gain of the complete receiver 34 shown in FIG. 4 is then given as per Equation 9 below:

[00009]$\begin{array}{cc}\mathrm{Voltage}\mathrm{gain}\mathrm{of}\mathrm{the}\mathrm{complete}\mathrm{receiver}34\mathrm{shown}\mathrm{in}\mathrm{FIG}.4& \\ A_V=.Math.\frac{v_{\mathrm{OUT},I}}{v_{\mathrm{IN}}}.Math.={\mathrm{NG}}_{\mathrm{mLNA}}\frac{\sqrt{2}}{\pi }{R}_{\mathrm{TIA}}& \mathrm{Equation}9\end{array}$

where the factor of

[00010]$\frac{\sqrt{2}}{\pi }$

corresponds to a mixer conversion loss with a 25% LO duty cycle.

[0107] In the LNA 28 of the present invention, both of the transconductance amplifiers 30, 32 can each be implemented as a respective CMOS inverter, as shown in FIG. 13 with biasing details omitted, in which an NMOS transistor M.sub.1 and PMOS transistor M.sub.2 are arranged such that their gate terminals are connected together at an input node IN and their drain terminals are connected together at an output node OUT. The source terminal of the NMOS transistor M.sub.1 is typically connected to ground and the source terminal of the PMOS transistor M.sub.2 is typically connected to a positive supply rail V.sub.DD. The same inverter topology may be used for each amplifier 30, 32, but typically with different FET dimensions, bias currents, etc.

[0108] As discussed previously, in practice, the gates of the NMOS transistor M.sub.1 and the PMOS transistor M.sub.2 are typically biased at different gate voltages. However, when operated at RF frequencies (which is of interest in here), the CMOS inverter effectively looks as shown in FIG. 13.

[0109] The output impedance of the first transconductance amplifier 30 (G.sub.mLNA) at RF frequencies is usually much larger than the corresponding output impedance of a conventional CMOS RFB LNA.

[0110] In addition, at RF frequencies, it is usually the parasitic capacitance C.sub.P at the LNA output which limits both the LNA output impedance Z.sub.O,LNA at RF and the mixer output resistance R.sub.O,MIX at BB frequencies.

[0111] FIG. 6 is a circuit diagram of a model used to calculate the noise contribution of the TIA op-amps used with the radio receiver device of FIG. 4. Generally, where the analogue baseband (ABB) circuit following the mixer(s) is realized with ‘balanced’ (or ‘differential’) circuits, the signal can be considered to have both negative and positive ‘branches’. As a result, both the I and Q phase down-converted signals have both positive and negative ‘branches’.

[0112] In practice, the IQ mixers 38, 40 are driven by LO signals from the LO 42, where the LO signals have a 25% duty cycle. There are four constituent LO signals or ‘phases’, specifically wherein there is a positive and negative LO phase (a suffix of ‘P’ or ‘N’ respectively) for each of the in-phase and quadrature components (a suffix of ‘I’ or ‘0’ respectively): LO.sub.IP; LO.sub.QP; LO.sub.IN; and LO.sub.QN. The 25% duty cycle means that while a single LO phase is high, the other three LO phases are low. The behaviour of the circuit with respect to these four LO phases is described briefly in turn.

[0113] Firstly, the differential transconductance amplifier 30 provides differential RF current at its output, which is routed to the TIA 44 while the LO phase LO.sub.IP is high and all other LO phases are low. Secondly, while the LO phase LO.sub.QP is high and all other LO phases are low, the differential RF current of the transconductance amplifier 30 is routed to the TIA 46. Thirdly, while the LO phase LO.sub.IN is high and all other LO phases are low, the differential RF current of the transconductance amplifier 30 is routed to the TIA 44, but now with inversion compared to the case when LO.sub.IP was high. Finally, when the LO phase LO.sub.QN is high and all other LO phases are low, the differential RF current of the transconductance amplifier 30 is routed to the TIA 46, but now with inversion compared to the case when LO.sub.QP was high.

[0114] The output resistance of the passive current mode mixer in the direct conversion receiver 34 that employs the (differential) LNA 28 in accordance with an embodiment of the present invention can be analysed by considering the circuit shown in FIG. 6.

[0115] Due to the switched-capacitor (SC) effect, the parasitic capacitance (C.sub.P) at the output of the LNA 28 limits the mixer output resistance R.sub.OUT,MIX as per Equation 10 below:

[00011]$\begin{array}{cc}\mathrm{Mixer}\mathrm{output}\mathrm{resistance}{R}_{\mathrm{OUT},\mathrm{MIX}}& \\ R_{\mathrm{OUT},\mathrm{MIX}}=2\left(\frac{1}{4f_{\mathrm{LO}}{C}_P}+2R_{\mathrm{SW}}\right)& \mathrm{Equation}10\end{array}$

where f.sub.LO is the LO frequency or RF operation frequency and R.sub.SW is the ON-resistance of a single mixer switch.

[0116] In practice, the mixer output resistance with the LNA 28 of FIG. 3A having a transconductance stage (i.e. the first transconductance amplifier 30, G.sub.mLNA) with a large output impedance is much larger than the corresponding mixer output resistance with a conventional RFB (or CFB) LNA known in the art per se.

[0117] Accordingly, by employing the disclosed LNA in a direct conversion receiver, the noise contributions and DC-offsets of the TIAs can be reduced to a much lower level compared to a receiver in which the conventional RFB (or CFB) LNA is used.

[0118] With the disclosed architecture of the LNA 28, the actual amplifier (i.e. the first transconductance amplifier 30, G.sub.mLNA) driving the current mode mixers 38, 40 is realized as voltage-to-current amplifier (i.e. transconductance amplifier), which has large input and output resistance. Via frequency translation in the mixers 38, 40, the large output impedance of the LNA 28 is translated to a large current mode passive mixer output resistance, which lowers the noise and DC-offsets due to the TIAs 44, 46. In addition, via frequency translation by the current mode passive mixers 38, 40, the low input impedance of TIAs 44, 46 is translated to the mixer RF input and therefore to the output of the first transconductance amplifier 30, which improves the linearity of the LNA 28. That is, the out-of-band blocking signals create a small voltage swing at the output of the first transconductance amplifier 30, which improves the linearity of the entire receiver 34.

[0119] Similarly, the blocking signals presented at the input of the LNA 28 are amplified to the output of the second transconductance amplifier 32 but with much lower voltage gain compared to a conventional RFB or CFB LNA, which creates less compression at the output of the second transconductance amplifier 32. Moreover, because the CFB amplifier that provides the input matching appears in parallel with the actual signal path, its compression is much less concern compared to conventional RFB or CFB LNAs, in which the compression takes place at the signal path. As a result, the LNA of the present invention may achieve much higher linearity at low supply voltage compared to prior art RFB or CFB LNAs.

[0120] The off-chip impedance matching network 36 of FIGS. 5A and 5B is constructed from a parallel inductance L.sub.M and a series capacitor C.sub.M that transform the source resistance R.sub.S upwards to R.sub.EQ. That is, the impedance transformation ratio is N.sup.2 (see (20)) and the matching network amplifies the incoming RF voltage by a factor of N. It will of course be appreciated that this matching network 36 is only exemplary and other similar networks can be employed. The off-chip matching network 36 consisting of L.sub.M and C.sub.M is preferable to using an on-chip matching network, especially because the off-chip inductor L.sub.M can achieve a much higher Q-factor and lower loss compared to on-chip inductors used in conventional LNA arrangements. Accordingly, the LNA with off-chip matching network can achieve a lower NF than the LNA employing completely integrated input matching.

[0121] In the presented LNA 28 described above, the matching network transformation ratio N.sup.2 and voltage gain N are generally chosen to be sufficiently large so as to lower the NF of the LNA 28 and receiver 34, however too large a value of N may degrade the linearity of the LNA 28. As the value of N is chosen, the values of the respective transconductance values G.sub.mLNA and G.sub.mM of the first and second transconductance amplifiers 30, 32 are selected to obtain a desired NF for the LNA 28 and receiver, and to tune the voltage gain of the receiver 34. In addition, once N and G.sub.mM are known, the values for C.sub.EQ and R.sub.EQ may be determined.

[0122] In the passive off-chip matching network 36, the value of the off-chip matching inductor L.sub.M sets the input resistance of the LNA 28 to the source impedance R.sub.S. The value of L.sub.M can be approximated as per Equation 11 below:

[00012]$\begin{array}{cc}\mathrm{Inductance}\mathrm{of}\mathrm{passive}\hspace{1em}\mathrm{off}\text{-}\hspace{1em}\mathrm{chip}\mathrm{impedance}\mathrm{matching}\mathrm{network}36& \\ L_M=\frac{{\mathrm{NR}}_S}{{\omega }_0+{\omega }_0^2{C}_{\mathrm{EQ}}{\mathrm{NR}}_S}& \mathrm{Equation}11\end{array}$

where ω.sub.0 is the (angular) operation frequency and C.sub.EQ is the equivalent capacitance presented at the inputs of G.sub.mM and G.sub.mLNA (see Equation 2).

[0123] On the other hand, the value of the off-chip matching capacitor C.sub.M is chosen to cancel the imaginary part of the input impedance of the LNA 28 and to fulfil the following resonance condition at the frequency interest as per Equation 12:

[00013]$\begin{array}{cc}\mathrm{Resonance}\mathrm{condition}\mathrm{at}\mathrm{frequency}\mathrm{of}\mathrm{interest}& \\ {\omega }_0^2=\frac{1}{\left(C_M+C_{EQ}\right)L_M}& \mathrm{Equation}12\end{array}$

from which the value of the off-chip matching capacitor is given per Equation 13:

[00014]$\begin{array}{cc}\mathrm{Capacitance}\mathrm{of}\mathrm{passive}\hspace{1em}\mathrm{off}\text{-}\mathrm{chip}\mathrm{impedance}\mathrm{matching}\mathrm{network}36& \\ C_M=\frac{1}{{\omega }_0^2{L}_M}-C_{\mathrm{EQ}}& \mathrm{Equation}13\end{array}$

[0124] In principle, the matching network 36 consisting of two components of L.sub.M and C.sub.M is able to realise the LNA input matching only at the single operation frequency f.sub.0, or in practice at a relatively narrow frequency band. This can be seen from Equations 11 to 13, in which the calculated values for L.sub.M and C.sub.M are functions of ω.sub.0 and thus may vary at other frequencies.

[0125] In practice, the bandwidth, at which the LNA input matching is acceptable, depends on the desired impedance transformation ratio (N.sup.2). The large impedance matching ratio translates to the narrow input matching bandwidth and vice versa. Thus, in order to provide robust LNA input matching, the impedance matching ratio N.sup.2 may be capped at a maximum of around 10, resulting in reasonable matching bandwidth. However, modifications to the topology for multiband applications are described below.

[0126] FIGS. 7A and 7B are circuit diagrams of an LNA 128 for a multiband receiver 134. These arrangements make use of variable capacitors (or varactors) in order to tune the receiver 134 between different operating frequencies. Generally, these variable capacitors are capacitor matrices.

[0127] Firstly, the arrangement shown in FIG. 7A provides multiband operation by making the capacitance of the capacitors C.sub.1 and C.sub.2 in the capacitive feedback network variable. In particular, the values of C.sub.1 and C.sub.2 are configured in such a way that the ratio C.sub.1/(C.sub.1+C.sub.2) remains substantially constant while C.sub.EQ varies at different operation frequency bands. The constant value of C.sub.1/(C.sub.1−C.sub.2) provides the substantially constant value of R.sub.EQ (see Equation 1) and matching network voltage gain N at all frequency bands.

[0128] In order to achieve this, at the highest frequency band of interest, C.sub.EQ is set to its lowest value and the values for the matching components L.sub.M and C.sub.M are obtained from Equation 11 and Equation 13 respectively, and through simulation. After this, the values of L.sub.M and C.sub.M are fixed. Next, at the lower frequency bands, the value for C.sub.EQ is tuned (e.g. increased) so as to cancel the imaginary part of the input impedance of the LNA 128 and to tune the resonance of the input impedance of the LNA 128 to the corresponding (lower) operation frequency. In other words, for a given operation frequency with fixed L.sub.M and C.sub.M, the value for C.sub.EQ can be approximated from Equation 12 as per Equation 14 below:

[00015]$\begin{array}{cc}\mathrm{Equivalent}\mathrm{capacitance}{C}_{\mathrm{EQ}}\mathrm{for}a\mathrm{given}\mathrm{operation}\mathrm{frequency}& \\ C_{\mathrm{EQ}}=\frac{1}{{\omega }_0^2{L}_M}-C_M& \mathrm{Equation}14\end{array}$

[0129] Thus at the lower operation frequency bands, a higher value for C.sub.EQ is employed.

[0130] FIG. 7B shows an alternative approach in which a configurable capacitor C.sub.T is introduced at the input terminals of the first and second transconductance amplifiers 130, 132, and whose value is adjusted depending on the operation frequency. This technique also allows constant value of R.sub.EQ (see Equation 1) and matching network voltage gain N at all frequency bands. On the other hand, the values of the matching inductance L.sub.M and capacitance C.sub.M are now altered as per Equations 15 and 16 respectively:

[00016]$\begin{array}{cc}\mathrm{Matching}\mathrm{inductance}\mathrm{with}\mathrm{introduction}\mathrm{of}\mathrm{variable}\mathrm{capacitor}{C}_T& \\ L_M=\frac{{\mathrm{NR}}_S}{{\omega }_0+{\omega }_0^2\left(C_{\mathrm{EQ}}+C_T\right){\mathrm{NR}}_S}& \mathrm{Equation}15\\ \mathrm{Matching}\mathrm{capacitance}\mathrm{with}\mathrm{introduction}\mathrm{of}\mathrm{variable}\mathrm{capacitor}{C}_T& \\ C_M=\frac{1}{{\omega }_0^2{L}_M}-C_{\mathrm{EQ}}-C_T& \mathrm{Equation}16\end{array}$

[0131] In order to provide multiband operation, the approach with the arrangement of FIG. 7B is similar to that of FIG. 7A described above. At the highest frequency band of interest, C.sub.T is set to its lowest value and the values for the matching components L.sub.M and C.sub.M are obtained from Equations 15 and 16 above, and through simulation. Then, the values of L.sub.M and C.sub.M are fixed. At the lower frequency bands, the value for C.sub.T is tuned (e.g. increased) to cancel the imaginary part of the input impedance of the LNA 128 and to tune the resonance of the LNA input impedance to the corresponding operation frequency. For given operation frequency with fixed L.sub.M and C.sub.M, the value for C.sub.T can be approximated from Equation 16 as per Equation 17 below:

[00017]$\begin{array}{cc}\mathrm{Capacitance}\mathrm{of}{C}_T\mathrm{for}a\mathrm{given}\mathrm{operation}\mathrm{frequency}& \\ C_T=\frac{1}{{\omega }_0^2{L}_M}-C_M-C_{\mathrm{EQ}}& \mathrm{Equation}17\end{array}$

[0132] It can be seen that lower operation frequency bands require a higher value for C.sub.T.

[0133] Both of the LNA topologies shown in FIGS. 7A and 7B adjust a capacitance value to achieve multiband operation. In practice, adjusting the capacitance can be accomplished on-chip by using varactors (i.e. a capacitor where the capacitance can be adjusted with a control voltage, i.e. an active device) or switched matrices of passive capacitors, i.e. ‘capacitor matrices’. In many cases, switched matrices may be preferred as they are typically more linear than varactors. An example of such a switched capacitor matrix is described in further detail below with reference to FIG. 9B.

[0134] The capacitances of C.sub.1 and C.sub.2 may be determined as per Equations 18 and 19 below respectively:

[00018]$\begin{array}{cc}\mathrm{Capacitance}\mathrm{of}{C}_1& \\ C_1=\frac{C_2}{G_{\mathrm{mM}}{R}_{\mathrm{EQ}}-1}& \mathrm{Equation}18\\ \mathrm{Capacitance}\mathrm{of}{C}_2& \\ C_2=G_{\mathrm{mM}}{R}_{\mathrm{EQ}}{C}_{\mathrm{EQ}}& \mathrm{Equation}19\end{array}$

[0135] FIG. 8 is a circuit diagram of an LNA 228 in which the second transconductance amplifier 232 has an adjustable supply current and, therefore, adjustable transconductance. Such an arrangement may be particular beneficial for battery-operated devices, as outlined below.

[0136] In some applications, when receiving a very weak desired RF signal, the wireless receiver 234 may be operated in a ‘sensitivity mode’ in which it needs to display a low NF in order to provide sufficiently large SNR at the receiver output. Above the sensitivity level, however, the strength of the desired RF signal may be sufficiently large that NF requirements for the receiver 234 may be relaxed while still maintaining a sufficient SNR at the output of the receiver 234. As such, the wireless receiver device 234 may rely on automatic gain control, in which the receiver NF and gain is controlled based on the strength of the received signal.

[0137] In the presence of a sufficiently large desired signal at the input to the receiver 234 or LNA 228, the receiver 234 may be set to a ‘low power’ mode with higher NF (compared to the sensitivity mode) and its power consumption may be also scaled down. This may be especially advantageous for battery-operated device applications, in which low power consumption translates to long life-time of battery.

[0138] Accordingly, in the LNA 228 of FIG. 8, the supply current consumed by the second transconductance amplifier 232 that provides the LNA input matching can be varied. In particular, the transconductance (G.sub.mM) of the second transconductance amplifier 232 is scaled down while the level of the desired RF signal at the input of the LNA 228 is sufficiently large. Scaling down the value of the transconductance (G.sub.mM) of the second transconductance amplifier 232 also scales down the supply current, and thus the power consumption, of the second transconductance amplifier 232.

[0139] The actual scaling of the second transconductance amplifier 232 can be performed for instance by switching off parallel unit stages, which decreases the supply current consumed by the second transconductance amplifier 232 accordingly.

[0140] In the LNA 228 of FIG. 8, the scaling of this transconductance G.sub.mM is performed while keeping R.sub.EQ and C.sub.EQ constant, which advantageously leaves the LNA input matching and the gain of the matching network (N) unchanged as the current varies. When the value of the transconductance G.sub.mM of the second transconductance amplifier 232 is changed, the capacitance values of capacitors C.sub.1 and C.sub.2 may also need to be changed accordingly so as to ensure constant values of R.sub.EQ and C.sub.EQ. With a constant R.sub.EQ and C.sub.EQ, the values for capacitors C.sub.1 and C.sub.2 can be estimated from Equations 1 and 2 as G.sub.mM is varied.

[0141] In other words, if the transconductance G.sub.mM of the second transconductance amplifier 232 is changed, for example reduced, the values of both C.sub.1 and C.sub.2 must be changed in order leave R.sub.EQ and C.sub.EQ unchanged. This can be implemented using switched capacitor matrices, as shown in FIG. 8. As the LNA 228 shown in FIG. 8 employs configurable capacitor C.sub.T at the inputs of the transconductance amplifiers 230, 232, it is able to tune also to multiple frequency bands.

[0142] FIG. 9A is a circuit diagram illustrating the biasing used in an LNA 328 in accordance with an embodiment of the present invention. In the particular example shown, the LNA 328 is single-ended, however it may be of course be differential instead.

[0143] In particular, FIG. 9A shows a simplified circuit-level schematic of the second transconductance amplifier 332, in which only one setting for supply current is shown for simplicity. The second transconductance amplifier 332 is constructed as a CMOS inverter made from a PMOS transistor 300 and an NMOS transistor 301. The capacitors C.sub.1 and C.sub.2 form the capacitive feedback network and the sum of the respective transconductances of the saturation-region PMOS transistor 300 and NMOS transistor 301, i.e. g.sub.mPM and g.sub.mNM, equals the transconductance G.sub.mM of the second transconductance amplifier 332. The voltage V.sub.B is the DC gate bias voltage of the NMOS transistor 301.

[0144] The resistors R.sub.1 and R.sub.2 are biasing resistors having large resistance, and their resistance does not, in practice, affect the performance of the input matching circuit when the resistance is selected to be sufficiently large, e.g. 20 kΩ. Also provided are a pair of AC-coupling capacitors C.sub.3 and C.sub.4. The bias voltage V.sub.B and the dimensions of the NMOS device 301 define the supply current of the second transconductance amplifier 332 as the PMOS transistor 300 forms a diode-connected device with R.sub.1 from the biasing point of view or at DC. This ensures a well-defined DC voltage at the output node of the second transconductance amplifier 332 (i.e. at the drains of the CMOS transistors 300, 301). However, for RF signals at RF frequencies, both P- and NMOS transistors 300, 301 act as common-source amplifiers, forming a push-pull transconductance stage. The supply current may be minimised by using a push-pull structure with stacked PMOS and NMOS devices in the same current branch.

[0145] In the LNA 328 of FIG. 9A, the multiband operation or configurable operation frequency is implemented with a programmable capacitor matrix C.sub.T. An example of this capacitor matrix 350 is shown in FIG. 9B, which is a circuit diagram of a variable capacitor matrix for use in a multiband LNA. Although FIG. 9B is shown to illustrate a variable capacitor C.sub.T, a similar topology can be used to implement adjustable values for C.sub.1 and C.sub.2 used in the capacitive feedback in embodiments that employ such variable capacitors for those components, e.g. as shown in FIG. 7A.

[0146] In this arrangement, the capacitor matrix 350 uses three control bits (C<2:0>) and a fixed capacitance of N.Math.C.sub.LSB (LSB=least significant bit) is shown as an example. All of the capacitors are implemented as multiple units of C.sub.LSB.

[0147] The capacitor matrix 350 shown as an example in FIG. 9B allows for eight different values of capacitance and accordingly, eight different values can be set for the operation frequency. For example, when all of the controls bits are high (C<2:0>=‘111’), all three of the control NMOS switches 303a-c conduct and the total capacitance is C.sub.T=(7+N)C.sub.LSB. This corresponds to the lowest operation frequency. On the other hand, when all controls bits are low (C<2:0>=‘0001’) all the three control NMOS switches 303a-c are not conducting and the total capacitance is C.sub.T=NC.sub.LSB. With this setting, the highest operation frequency is set. Of course, operation frequencies in between these extremes may be achieved by setting some but not all of the three control NMOS switches 303a-c to conduct.

[0148] FIG. 10 is a circuit diagram of an LNA 428 having two different power modes. The resistors R.sub.1-R.sub.4 are biasing resistors having large resistance, the capacitors C.sub.3 to C.sub.6 are AC-coupling capacitances, and M.sub.5 to M.sub.8 are controls switches.

[0149] When the control voltage V.sub.C is high or V.sub.C=V.sub.DD, both of the parallel branches are active, providing the maximum value of the transconductance G.sub.mM=(g.sub.mNM,1+g.sub.mNM,2+g.sub.mPM,1+g.sub.mPM,2) of the second transconductance amplifier 432 and, therefore, a low NF. In this mode, the switch transistors M.sub.6 and M.sub.7 are closed (conducting) and M.sub.5 and M.sub.8 are open.

[0150] When V.sub.C is low or V.sub.C=0 V, one branch is switched off, which decreases the supply current at the expense of higher NF. In this mode, M.sub.5 and M.sub.8 are closed (conducting) and M.sub.6 and M.sub.7 are open. The gates of M.sub.3 and M.sub.4 are connected to 0 V and V.sub.DD, respectively, thereby switching these two devices off and decreasing the supply current accordingly. In this mode, the transconductance of the second transconductance amplifier 432 G.sub.mM=(g.sub.mNM,1+g.sub.mPM,1) and the values of C.sub.1 and C.sub.2 need to be adjusted according to Equations 18 and 19 above.

[0151] The mode with lower supply current and higher NF could be used when the desired signal is not near the sensitivity level and a higher receiver and LNA NF can be tolerated. In FIG. 10, NMOS and PMOS switches are shown for simplicity, however in practice these could be replaced with CMOS switches, or NMOS devices could be replaced with PMOS transistors, and vice versa, depending on the particular implementation in use e.g. biasing, supply, and transistor threshold voltages, etc. Although only two modes of operation are shown, more than two modes can be implemented by adding more switched parallel CMOS stages.

[0152] FIG. 11 is a circuit diagram of a single-ended multiband LNA 528 with programmable supply current employed in an on-chip inductor-less radio receiver 534 with single-balanced passive current-mode IQ down conversion mixers 538, 540. As with the other LNA architectures described herein, the LNA of FIG. 11 can be realised both as either a single-ended or differential circuit as required.

[0153] The multiband operation is achieved with switched capacitor matrix C.sub.T and the supply current of the input matching circuit can be adjusted according to the power of desired RF input signal with a second transconductance amplifier having a programmable transconductance G.sub.mM and switched capacitor matrices C.sub.1 and C.sub.2 in the capacitive feedback network, as described previously.

[0154] A programmable voltage gain in the receiver can be implemented in the actual amplifying transconductance stage, i.e. the first transconductance amplifier 530 can have a programmable transconductance G.sub.mLNA, as is indicated with an arrow. The capacitor C.sub.3 is an AC-coupling capacitor, which is advantageous when the DC voltages at the LNA output and mixer input are not necessarily the same, and this capacitor C.sub.3 may also attenuate any low-frequency 2.sup.nd order intermodulation distortion generated in the stages before the down conversion mixers 538, 540, which in turn drive the TIAs 544, 546. The capacitor C.sub.3 also prevents any DC current flowing to the passive mixer switches, which is important to ensure that the mixer switches do not generate any flicker noise. The input impedance matching network 536 components are off-chip for low loss and low NF. Advantageously, only a single RF input package pin is needed in this receiver 534.

[0155] FIG. 12 is a circuit diagram of a differential multiband LNA 628 with programmable supply current employed in an on-chip inductor-less radio receiver with double-balanced passive current-mode IQ down conversion mixers. The LNA 628 includes: transconductance amplifiers 630, 632; mixers 638, 640; and TIAs 644, 646, which operate in a similar manner to the corresponding components outlined above.

[0156] For ease of description and explanation, the transconductance amplifiers for both the positive and negative branches are described together as they are identical in structure and function.

[0157] In the receiver 634 of FIG. 12, multiband operation is achieved with differential switched capacitor matrix C.sub.TD. The supply current provided to the input matching circuit can be adjusted according to the power of desired RF input signal with a programmable second transconductance amplifiers 632 and switched capacitor matrices C.sub.1P, C.sub.2P, C.sub.1N, and C.sub.2N in the parallel CFB amplifiers.

[0158] A programmable voltage gain in the receiver can be implemented in the actual amplifying transconductance stages—i.e. the first transconductance amplifiers 630 having respective transconductances G.sub.mLNAP and G.sub.mLNAN—as indicated with arrows, where the indices P and N refer to positive and negative branches, respectively.

[0159] The capacitors C.sub.3P and C.sub.3N are AC-coupling capacitors as discussed previously.

[0160] The off-chip matching network 636 are constructed from series capacitors C.sub.MP and C.sub.MN and parallel inductance L.sub.MD. Two RF input package pins may be required in this receiver and the number of off-chip components is increased from two to three due to the additional off-chip capacitor.

[0161] Thus it will be appreciated by those skilled in the art that embodiments of the present invention provide an on-chip inductor-less LNA architecture for wireless receivers. In the disclosed LNA topology, the LNA input matching is realised with the parallel CFB amplifier while another transconductance amplifier drives the current mode passive mixers with voltage-to-current conversion gain. As the receiver RF amplifying stage is implemented as a true transconductance amplifier (G.sub.mLNA) with a large output impedance, a large passive current mode mixer output resistance is achievable, which may minimise the noise and DC offsets of the BB TIAs. Embodiments of the present invention may achieve a relatively high level of linearity at low supply voltages.

[0162] Those skilled in the art will appreciate that the specific embodiments described herein are merely exemplary and that many variants within the scope of the invention are envisaged.