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A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) in a selected manner through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth and the particles for a pattern at the selected depth. An energy source such as pressurized fluid is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

An unassembled simple matrix liquid crystal display (LCD) panel, with strips of highly-conductive material, is tested by extracting a two-dimensional image of the capacitance distribution across the surface of the panel under test (PUT) through illumination of a modulator placed adjacent the surface, such as an NCAP modulator or other liquid dispersed polymer-based device. The light modulator is disposed to allow longitudinal probing geometries such that a measurement of capacitance is developed across a gap between the surface of the panel under test and the opposing face of the modulator which causes a power modulation in the optical energy which can be observed through an area optical sensor (such as a camera) for use in directly produce a two-dimensional spatially-dependent power modulation image directly representative of the spatially corresponding capacitance state on the surface of the panel under test.

Circuit panels, such as LCD panels, are inspected in-process and after final assembly to identify defects. Prior to final assembly, panels identified as having sufficiently few defects are repaired. Similarly after final assembly, panels identified as having sufficiently few defects are repaired. The inspection and repair systems are linked through a repair file. The inspection system identifies each defect by type and location and includes such information in the repair file. The repair system accesses such file and follows a prescribed repair method for a given type of defect at the location of such defect. Simple matrix panel defects include open line defects and line to line shorts. The inspection system includes an automated non-contact capacitance imaging system. The repair system may include a pair of lasers and a film dispenser. A first laser is used to selectively remove material and cut lines. The dispenser is for applying a liquid organic metallic film in the defect area. The second laser is for tracing a line in the film to form a conductive path repairing the defect.

A hierarchical testing method is implemented taking advantage of the nature of the most common defects in an LCD panel to achieve fast effective parametric testing of LCD panels and the like. At the first hierarchy of testing, the panel is logically divided into zones and each zone tested in isolation to identify zones having at least one defect. At the next hierarchy, electro-optic assisted zone inspection is performed to identify where within the zone the defects are located. Lastly, every pixel is inspected using a voltage imaging method to determine whether the switching integrity of the pixel is acceptable. The testing apparatus includes a plurality of panel interface devices coupling the panel under test's drive lines and gate lines to a precision measurement unit (PMU). A controller determines the PMU signals and configures the panel interface devices. The PMU monitors select drive lines and gate lines to isolate zones having defects. An electro-optic voltage measurement system is used to identify the location of defects within an isolated zone.

A hierarchical testing method is implemented taking advantage of the nature of the most common defects in an LCD panel to achieve fast effective parametric testing of LCD panels and the like. At the first hierarchy of testing, the panel is logically divided into zones and each zone tested in isolation to identify zones having at least one defect. At the next hierarchy, electro-optic assisted zone inspection is performed to identify where within the zone the defects are located. Lastly, every pixel is inspected using a voltage imaging method to determine whether the switching integrity of the pixel is acceptable. The testing apparatus includes a plurality of panel interface devices coupling the panel under test's drive lines and gate lines to a precision measurement unit (PMU). A controller determines the PMU signals and configures the panel interface devices. The PMU monitors select drive lines and gate lines to isolate zones having defects. An electro-optic voltage measurement system is used to identify the location of defects within an isolated zone.

A method of fabricating a thickness of silicon material includes providing a silicon ingot material having a surface region and introducing a plurality of particles having an energy of about 1-5 MeV through the surface region to a depth to define a cleave region and a thickness of detachable material between the cleave region and the surface region. Additionally, the method includes processing the silicon ingot material to free the thickness of detachable material at a vicinity of the cleave region and causing formation of a free-standing thickness of material characterized by a carrier lifetime about 10 microseconds and a thickness ranging from about 20 microns to about 150 microns with a thickness variation of less than about five percent. Furthermore, the method includes treating the free-standing thickness of material using a thermal treatment process to recover the carrier lifetime to about 200 microseconds and greater.

A method for forming a strained silicon layer of semiconductor material. The method includes providing a deformable surface region having a first predetermined radius of curvature, which is defined by R(1) and is defined normal to the surface region. A backing plate is coupled to the deformable surface region to cause the deformable surface region to be substantially non-deformable. The method includes providing a first substrate (e.g., silicon wafer) having a first thickness. Preferably, the first substrate has a face, a backside, and a cleave plane defined within the first thickness. The method includes a step of overlying the backside of the first substrate on a portion of the surface region having the predetermined radius of curvature to cause a first bend within the thickness of material to form a first strain within a portion of the first thickness. The method provides a second substrate having a second thickness, which has a face and a backside. The method includes a step of overlying the face of the second substrate on a portion of the face of the first substrate to cause a second bend within the thickness of material to form a second strain within a portion of the second thickness. A step of joining the face of the second substrate to the face of the first substrate form a sandwich structure while maintaining the first bend in the first substrate and the second bend in the second substrate. Preferably, joining occurs using a low temperature process such as plasma activated bonding or the like.

A method for forming a strained layer of semiconductor material, e.g., silicon, germanium, Group III/V, silicon germanium alloy. The method includes providing a non-deformable surface region having a first predetermined radius of curvature, which is defined by R(1) and is defined normal to the surface region. The method includes providing a first substrate (e.g., silicon wafer) having a first thickness. Preferably, the first substrate has a face, a backside, and a cleave plane defined within the first thickness. The method includes a step of overlying the backside of the first substrate on a portion of the surface region having the predetermined radius of curvature to cause a first bend within the thickness of material to form a first strain within a portion of the first thickness. The method provides a second substrate having a second thickness, which has a face and a backside. The method includes a step of overlying the face of the second substrate on a portion of the face of the first substrate to cause a second bend within the thickness of material to form a second strain within a portion of the second thickness. A step of joining the face of the second substrate to the face of the first substrate form a sandwich structure while maintaining the first bend in the first substrate and the second bend in the second substrate. Preferably, joining occurs using a low temperature process such as plasma activated bonding or the like.

A method for forming a strained layer of semiconductor material, e.g., silicon, germanium, Group III/V, silicon germanium alloy. The method includes providing a non-deformable surface region having a first predetermined radius of curvature, which is defined by R(1) and is defined normal to the surface region. The method includes providing a first substrate (e.g., silicon wafer) having a first thickness. Preferably, the first substrate has a face, a backside, and a cleave plane defined within the first thickness. The method includes a step of overlying the backside of the first substrate on a portion of the surface region having the predetermined radius of curvature to cause a first bend within the thickness of material to form a first strain within a portion of the first thickness. The method provides a second substrate having a second thickness, which has a face and a backside. The method includes a step of overlying the face of the second substrate on a portion of the face of the first substrate to cause a second bend within the thickness of material to form a second strain within a portion of the second thickness. A step of joining the face of the second substrate to the face of the first substrate form a sandwich structure while maintaining the first bend in the first substrate and the second bend in the second substrate. Preferably, joining occurs using a low temperature process such as plasma activated bonding or the like.