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Patent Abstract
Microprocessor and data flow microprocessor having vector operation function
Patent number: 5666535
Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP)
Inventors: Shinji Komori (Itami, JP), Hidehiro Takata (Itami, JP), Toshiyuki Tamura (Itami, JP), Fumiyasu Asai (Itami, JP), Hirono Tsubota (Itami, JP)

A microprocessor which can execute a test and set instruction for an exclusive control by combination of a few simple instructions, and data flow microprocessor which realizes high operation performance mainly in vector operation by reading out of data to be operated, writing in operation result and executing memory access in short time period and in parallel, and whose running efficiency of program is high in multi-processor construction.

Tag Data processing apparatus for a data flow computer
Patent number: 4841436
Assignee: Matsushita Electric Industrial Co., Ltd. (Kadoma, JP), Sanyo Electric Co., Ltd. (Moriguchi, JP), Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP), Sharp Corporation (Osaka, JP)
Inventors: Hajime Asano (Toyonaka, JP), Hiroaki Terada (Suita, JP), Katsuhiko Asada (Amagasaki, JP), Hiroaki Nishikawa (Suita, JP), Masahisa Shimizu (Kadoma, JP), Hiroki Miura (Hirakata, JP), Kenji Shima (Nishinomiya, JP), Shinji Komori (Itami, JP), Souichi Miyata (Shiki, JP), Satoshi Matsumoto (Uda, JP)

A tag data processing apparatus is described for use in a data flow computer utilizing a tagged token scheme. A tag adding process and tag restoring process are executed by using pipeline registers, a queue memory and simple control circuit, thereby obtaining high speed operation and superior throughput without the need for a tag memory table, complicated operation-test circuitry or a sequence control circuit.

Data flow processor with next destination node determination
Patent number: 5218706
Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP)
Inventors: Shinji Komori (Itami, JP), Hirono Tsubota (Itami, JP), Kenji Shima (Amagasaki, JP)

A data flow processor which is so constructed that the destination node number in a program memory is stored at a relative address from, for example, a stored address of the present instruction, and a storing address for the next instruction is obtained by adding the relative address of the next instruction to the address of the present instruction. Hence, an amount of data of storing address of instruction to be executed next executed and included in the respective instructions is reduced, whereby an amount of hardware at the program memory is reduced and the memory access time is contracted.

Data flow processor with data processing and next address determination being made in parallel
Patent number: 5363491
Assignee: Mitsubishi Denki Kabushiki Kaisha (JP)
Inventors: Shinji Komori (Itami, JP), Hirono Tsubota (Itami, JP), Kenji Shima (Amagasaki, JP)

A data flow processor which is so constructed that the destination node number in a program memory is stored at a relative address from, for example, a stored address of the present instruction, and a storing address for the next instruction is obtained by adding the relative address of the next instruction to the address of the present instruction. Hence, an amount of data of storing address of instruction to be executed next and included in the respective instructions is reduced, whereby an amount of hardware at the program memory is reduced and the memory access time is contracted.

Microprocessor and data flow microprocessor having vector operation function
Patent number: 5404553
Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP)
Inventors: Shinji Komori (Itami, JP), Hidehiro Takata (Itami, JP), Toshiyuki Tamura (Itami, JP), Fumiyasu Asai (Itami, JP), Hirono Tsubota (Itami, JP)

A microprocessor which can execute a test and set instruction for an exclusive control by combination of a few simple instructions, and data flow microprocessor which realizes high operation performance mainly in vector operation by reading out of data to be operated, writing in operation result and executing memory access in short time period and in parallel, and whose running efficiency of program is high in multi-processor construction.