H10F10/00

Networks and tethers using fiber reinforced high temperature superconductors
12255014 · 2025-03-18 · ·

A device comprises a support net with nodes, wherein each node comprises a HTS photovoltaic-magnetic cell, wherein alignments of the HTS photovoltaic-magnetic cells are arranged with N-S in parallel alignment. A device comprises a tether comprising a plurality of HTS solenoids and a sheath, wherein a solenoid of the plurality of HTS solenoids comprises a high temperature superconducting material and reinforcing fiber. A device comprises propulsion ball or plate with tail, injected in propulsion channel; HTS solenoids disposed along walls of propulsion channel, wherein the propulsion ball or plate with tail are moved through the propulsion channel using magnetic field generated by HTS solenoids; and a collection channel.

Solar cell emitter region fabrication using self-aligned implant and cap
09577134 · 2017-02-21 · ·

Methods of fabricating solar cell emitter regions using self-aligned implant and cap, and the resulting solar cells, are described. In an example, a method of fabricating an emitter region of a solar cell involves forming a silicon layer above a substrate. The method also involves implanting, through a stencil mask, dopant impurity atoms in the silicon layer to form implanted regions of the silicon layer with adjacent non-implanted regions. The method also involves forming, through the stencil mask, a capping layer on and substantially in alignment with the implanted regions of the silicon layer. The method also involves removing the non-implanted regions of the silicon layer, wherein the capping layer protects the implanted regions of the silicon layer during the removing. The method also involves annealing the implanted regions of the silicon layer to form doped polycrystalline silicon emitter regions.

POWER-MODULE SUBSTRATE, HEAT-SINK-ATTACHED POWER-MODULE SUBSTRATE, AND HEAT-SINK-ATTACHED POWER MODULE

A power-module substrate including a circuit layer having a first aluminum layer bonded on one surface of a ceramic substrate and a first copper layer bonded on the first aluminum layer by solid-phase-diffusion bonding, and a metal layer having a second aluminum layer made from a same material as the first aluminum layer and bonded on the other surface of the ceramic substrate and a second copper layer made from a same material as the first copper layer and bonded on the second aluminum layer by solid-phase-diffusion bonding, in which a thickness t1 of the first copper layer is 1.7 mm to 5 mm, a sum of the thickness t1 of the first copper layer and a thickness t2 of the second copper layer is 7 mm or smaller, and a ratio t2/t1 is larger than 0 and 1.2 or smaller except for a range of 0.6 to 0.8.

Nanostructured Hybrid-Ferrite Photoferroelectric Device
20170040473 · 2017-02-09 · ·

A photovoltaic device is fabricated using nanostructured hybrid ferrite materials with interdigital electrodes. The device includes ferrimagnetic ferrite nanopartides having a tunable narrow bandgap of 2.5 eV or less, which are deposited onto a thin ferroelectric film. The device produces an ultrahigh photocurrent density of 13-15 mA/cm.sup.2 when illuminated with sunlight of 100 mW/cm.sup.2, which is comparable to that of organic or silicon-based solar cells.

METHOD FOR MANUFACTURING LIGHT ABSORPTION LAYER OF THIN FILM SOLAR CELL AND THIN FILM SOLAR CELL USING THE SAME

A method for manufacturing a light absorption layer of a thin film solar cell includes: manufacturing a Ib group element-VIa group element binary system nano particle; manufacturing a binary system nano particle slurry of the Ib group element-VIa group element by adding a solution precursor including a solvent, binder and Va group element to the Ib group element-VIa group element binary system nano particle; distributing and mixing the binary system nano particle slurry of the Ib group element-VIa group element; coating the binary system nano particle slurry of the Ib group element-VIa group element on the rear electrode layer; and performing a heat treatment process on the coated nano particle slurry by supplying the VIa group element.

Integrated Photovoltaic Panel Circuitry
20250125767 · 2025-04-17 ·

A photovoltaic module is presented, which may include a photovoltaic panel and a converter circuit having a primary input connected to the photovoltaic panel and a secondary output galvanically isolated from the primary input. The primary input may be connectible to multiple input terminals within a junction box and at least one of the input terminals may be electrically connected to a ground. The photovoltaic module may include multiple interconnected photovoltaic cells connected electrically to multiple connectors (for example bus-bars). The photovoltaic module may include input terminals operable for connecting to the connectors and an isolated converter circuit. The isolated converter circuit may include a primary input connected to the input terminals and a secondary output galvanically isolated from the primary input.

Integrated Photovoltaic Panel Circuitry
20250125767 · 2025-04-17 ·

A photovoltaic module is presented, which may include a photovoltaic panel and a converter circuit having a primary input connected to the photovoltaic panel and a secondary output galvanically isolated from the primary input. The primary input may be connectible to multiple input terminals within a junction box and at least one of the input terminals may be electrically connected to a ground. The photovoltaic module may include multiple interconnected photovoltaic cells connected electrically to multiple connectors (for example bus-bars). The photovoltaic module may include input terminals operable for connecting to the connectors and an isolated converter circuit. The isolated converter circuit may include a primary input connected to the input terminals and a secondary output galvanically isolated from the primary input.

Integrated circuit devices including a metal resistor and methods of forming the same

Integrated circuit devices including a metal resistor and methods of forming the same are provided. The integrated circuit devices may include a substrate including a first surface and a second surface that is opposite the first surface and is parallel to the first surface, a transistor including a gate electrode, first and second resistor contacts that are spaced apart from each other in a horizontal direction that is parallel to the second surface of the substrate, and a metal resistor. The first surface of the substrate may face the gate electrode. The metal resistor may include a third surface and a fourth surface that is parallel to the third surface and the second surface of the substrate, and the fourth surface of the metal resistor may be closer to the second surface than the first surface and contacts the first and second resistor contacts.

Nano-metal connections for a solar cell array
12369409 · 2025-07-22 · ·

An electrical connection is formed between first and second conductive elements, by inserting a nano-metal material between the first and second conductive elements; and heating the nano-metal material to a melting temperature to form the electrical connection between the first and second conductive elements. The nano-metal material may comprise a nano-metal paste or ink comprised of one or more of Gold (Au), Copper (Cu), Silver (Ag), and/or Aluminum (Al) nano-particles that melt or fuse into a solid to form the electrical connection, at a melting temperature of about 150-250 degrees C., and more preferably, about 175-225 degrees C. The electrical connection may be formed between a solar cell and a substrate by creating a via in the solar cell between a front and back side of the solar cell, wherein the via is connected to a contact on the front side of the solar cell and a trace on the substrate.

Method for improving alignment between selective emitter and metal printing

A method for improving alignment between a selective emitters and metal printing, including: providing silicon wafer including first edge and midline parallel to the first edge; texturing and diffusing surface of the silicon wafer; and illuminating the surface of the silicon wafer by laser spots to form the SE. Multiple laser spots are arranged between the first edge and the midline to form spot rows, extension directions of the spot rows are parallel to the first edge, M spot rows are arranged and M is a positive integer and M>1. The M spot rows include N sub-spot regions, N is a positive integer and 1<NM, the sub-spot regions include at least one spot row, and areas of the laser spots in each sub-spot region are equal. The areas of the laser spots in different sub-spot regions from the midline pointing to the first edge gradually increases.