A method of forming a portion of a gate-all-around field-effect transistor (GAA FET) nanosheet structure includes performing a trim back recess process to form recesses in inner spacers of a fin-shaped column in a first direction from a sidewall of the fin-shaped column, wherein the fin-shaped column includes a stack of nanosheet channels and sacrificial layers having the inner spacers on both sides thereof in the first direction, performing an interface epitaxial growth process to grow interface source/drain (S/D) epi layers from exposed surfaces of the nanosheet channels of the fin-shaped column on the sidewalls of the fin-shaped column, performing an etch back process to etch back the interface S/D epi layer and form a continuous surface of the interface S/D epi layer, and performing a full epitaxial growth process to fully grow an S/D epi layer from the continuous surface of the interface S/D epi layer.

The present disclosure relates to a semiconductor package. The semiconductor package includes a semiconductor die and a plurality of leads. The plurality of leads includes two drain leads connected to the drain, two source leads connected to the source, a gate lead connected to the gate, the gate lead positioned between the two source leads, and a sensing lead positioned between the two source leads. The two source leads, the gate lead, and the sensing lead are positioned on a first side of the semiconductor package that is opposite to a second side of the semiconductor package, and wherein the drain leads are positioned on the second side.

The present disclosure relates to a semiconductor package with a pre-formed die clip and lead frame. The semiconductor package includes a semiconductor die, a heat spreader on a first side of the semiconductor die, a lead frame on a second side of the semiconductor die, and a die clip positioned between the semiconductor die and a portion of the lead frame. The die clip and the lead frame are pre-joined by way of various connection points.

The present disclosure relates to a semiconductor package. The semiconductor package includes a semiconductor die, molding material, and a conductive structure. The conductive structure is at least partly stacked with the semiconductor die, and the conductive structure includes a plurality of slots positioned around a point of the semiconductor die. The plurality of slots is configured to equalize thermal stresses during the operation of the semiconductor die about the point of the semiconductor die, where the thermal stresses are associated with coefficient of thermal expansion mismatches between the conductive structure and the molding material. In addition, at least a portion of the molding material is in contact with the conductive structure.

A method for a photon induced conductive material deposition on a substrate is provided. The method includes steps as follows: preparing a first solution comprising metalate, metal ions, or combinations thereof; preparing a first suspension comprising nanoparticles, a light sensitive reducing agent, an electron providing solvent, or combinations thereof; mixing the first solution and the first suspension to form a first reagent on a first substrate; and emitting a light beam provided by a light source and focusing the same onto the first reagent kept on a first region of the first substrate, so as to form a mechanically rigid conductive deposition in contact with the first substrate in a focus point of the light source, wherein the first substrate has a second region exposed to surrounding gas or an air environment.

The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first gate region, a first fin structure over the substrate in the first gate region. The first fin structure includes an upper semiconductor material member, a lower semiconductor material member, surrounded by an oxide feature and a liner wrapping around the oxide feature of the lower semiconductor material member, and extending upwards to wrap around a lower portion of the upper semiconductor material member. The device also includes a dielectric layer laterally proximate to an upper portion of the upper semiconductor material member. Therefore the upper semiconductor material member includes a middle portion that is neither laterally proximate to the dielectric layer nor wrapped by the liner.

An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to said buried region.

A semiconductor device is provided. The semiconductor device includes a substrate, a contact layer, and an active layer. The contact layer is located on the substrate. The contact layer and a movable object perform a relative motion. The active layer is located between the contact layer and the substrate.

An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to said buried region.

An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or siring includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.