A semiconductor device fabrication method may comprise: alternately and sequentially stacking a source/drain electrode layer forming a source/drain and a channel layer forming an oxide semiconductor channel; stacking a mask layer to surround a portion where a source/drain region is to be formed; exposing a channel layer of a channel region by etching and removing the source/drain electrode layer of the channel region exposed through the mask layer; and sequentially forming a gate dielectric layer and at least one gate electrode layer on the exposed channel layer of the channel region and on exposed lateral sides of the source/drain electrode layer of the source/drain region.

A semiconductor device includes channel members vertically stacked, a gate dielectric layer wrapping around each of the channel members, a first work function (WF) layer disposed over the gate dielectric layer and wrapping around each of the channel members, a first WF isolation layer disposed over the first WF layer, a second WF layer disposed over the first WF isolation layer, a second WF isolation layer disposed over the second WF layer, and a metal fill layer disposed over the second WF isolation layer. The first WF layer has a uniform thickness. The second WF isolation layer is a nitride-containing layer.

A method can include receiving a first power supply voltage at a first terminal at a first side of an IC device and providing a row of stacked pairs of insulated gate field effect transistor (IGFETs) substantially at the second side of the IC device. Each stacked pair can include a first and second IGFET of different conductivity types. Each IGFET can include multiple channels and a control gate that substantially surrounds the channels. A first power supply can be coupled from the first power supply terminal to a first source of one IGFET of the stacked pair via a first conductive via disposed between the first side and the second side and a first conductive line buried in and proximate the second side below the row of stacked pairs. Corresponding devices and systems are also disclosed.

A nanosheet semiconductor device includes channel nanosheets each connected to a source/drain region that has a front surface, a rear surface, and an internal recess between the front surface and the rear surface. The device further includes a source/drain region contact in physical contact with the V shaped internal recess, with the front surface, and with the rear surface. The device may be fabricated by forming the source/drain region, recessing the source/drain region, and by forming a sacrificial source/drain region upon and around the recessed source/drain region. The sacrificial source/drain region may be removed and the source/drain region contact may be formed in place thereof.

A method for fabricating a semiconductor device is provided. The method includes forming a fin structure extending along a first lateral direction; forming a dummy gate structure that is over a portion of the fin structure and extends along a second direction perpendicular to the first lateral direction; growing source/drain structures that are respectively coupled to ends of the portion of the fin structure; removing the dummy gate structure to form a gate trench; lining inner sidewalls of the gate trench with a gate spacer; and forming an active gate structure in the gate trench.

Methods for fabricating semiconductor structures are provided. An exemplary method includes forming a first transistor structure and a second transistor structure over a substrate, wherein each transistor structure includes at least one nanosheet. The method further includes depositing a metal over each transistor structure and around each nanosheet; depositing a coating over the metal; depositing a mask over the coating; and patterning the mask to define a patterned mask, wherein the patterned mask lies over a masked portion of the coating and the second transistor structure, and wherein the patterned mask does not lie over an unmasked portion of the coating and the first transistor structure. The method further includes etching the unmasked portion of the coating and the metal over the first transistor structure using a dry etching process with a process pressure of from 30 to 60 (mTorr).

An integrated circuit device includes: a fin-type active region on a substrate; a nanosheet disposed on the fin-type active region; a gate line surrounding the nanosheet, wherein the gate line overlaps the nanosheet; a source/drain region disposed on the fin-type active region and contacting the nanosheet; and an interface insulating film surrounding the gate line, and including an inner spacer portion disposed between a sidewall of the gate line and the source/drain region, wherein the inner spacer portion includes: a first inner spacer portion protruding toward the source/drain region, while covering the sidewall of the gate line and while spaced apart from the nanosheet, wherein the first inner spacer portion has a first thickness; and a second inner spacer portion extending from the first inner spacer portion toward the nanosheet, wherein the second inner spacer portion has a second thickness that is less than the first thickness.

The disclosure relates to a complementary field effect transistor, CFET, structure. The CFET structure comprises: a first CFET element which is arranged in a first row of the CFET structure; and a second CFET element which is arranged in a second row of the CFET structure, wherein the second row is arranged laterally offset to the first row; wherein the first and the second CFET element each comprise: a first transistor structure, and a second transistor structure which is arranged above the first transistor structure. The CFET structure further comprises a shared signal routing structure which is arranged between the first and the second CFET element; wherein the shared signal routing structure is electrically connected to the first and/or the second transistor structure of the first and/or of the second CFET element, respectively.

The present invention discloses a neuron and a neuromorphic system including the same. The neuron according to an embodiment of the present invention includes a two-terminal spin device for performing integration and fire, and the two-terminal spin device is formed to have a negative differential resistance (NDR) region in which current decreases as voltage increases.

The present invention discloses a neuron and a neuromorphic system including the same. The neuron according to an embodiment of the present invention includes a two-terminal spin device for performing integration and fire, and the two-terminal spin device is formed to have a negative differential resistance (NDR) region in which current decreases as voltage increases.