A device comprising two transistors stacked along a main direction, the first transistor comprising channels stacked along the main direction and first source and drain contacts, the second transistor comprising channels stacked along the main direction and second source and drain contacts, wherein the first source (respectively drain) contact and the second source (respectively drain) contact are distinct and isolated from one another by a first gate dielectric layer and by a second gate dielectric layer. The invention also relates to a method for manufacturing the device.

IC devices with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as angled if a longitudinal axis of an elongated semiconductor structure (e.g., a fin or a nanoribbon) based on which the transistor is built is at an angle other than 0 degrees or 90 degrees with respect to edges of front or back faces of a support structure on/in which the transistor resides, e.g., at an angle between 10 degrees and 80 degrees with respect to at least one of such edges. Angled transistors provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips.

In some embodiments, the present disclosure relates to an integrated chip including a gate electrode over a substrate. A pair of source/drain regions are disposed in the substrate on opposing sides of the gate electrode. A dielectric layer is over the substrate. An etch stop layer is between the gate electrode and the dielectric layer. A gate capping layer overlies the gate electrode, continuously extends from a top surface of the etch stop layer to a top surface of the gate electrode, and comprises a curved sidewall over the top surface of the etch stop layer. A conductive contact overlies an individual source/drain region. A width of the conductive contact continuously decreases from a top surface of the conductive contact to a first point disposed above a lower surface of the gate capping layer. The conductive contact extends along the curved sidewall of the gate capping layer.

A method includes forming a first dielectric layer over a substrate; forming a first transistor over a first side of the first dielectric layer; removing the substrate to expose a second side of the first dielectric layer opposite to the first side of the second dielectric layer; and forming a second transistor over the second side of the first dielectric layer. Forming the first transistor includes forming a semiconductor layer over the first side of the first dielectric layer; forming a first gate structure over the semiconductor layer; and forming source/drain epitaxy structures on opposite sides of the first gate structure. Forming the second transistor includes forming a semiconductive oxide layer over the second side of the first dielectric layer; forming a second gate structure over the semiconductive oxide layer; and forming source/drain contacts over the semiconductive oxide layer and on opposite sides of the second gate structure.

A semiconductor device includes a first active region defined on a substrate, a first gate electrode across the first active region, a first drain region in the first active region at a position adjacent to the first gate electrode, an undercut region between the first active region and the first gate electrode, and a first gate spacer on a side surface of the first gate electrode and extending into the undercut region.

A semiconductor structure includes a substrate, a first transistor disposed over the substrate and including a first channel, a first interfacial layer over the first channel, a first gate dielectric layer over the first interfacial layer, and a first gate electrode layer over the first gate dielectric layer, and a second transistor disposed over the substrate and including a second channel, a second interfacial layer over the second channel, a second gate dielectric layer over the second interfacial layer, and a second gate electrode layer over the second gate dielectric layer. The first gate dielectric layer includes a first dipole material composition having a first maximum concentration at a half-thickness line of the first gate dielectric layer. The second gate dielectric layer includes a second dipole material composition having a second maximum concentration at a half-thickness line of the second gate dielectric layer and greater than the first maximum concentration.

A semiconductor device and a method of forming the same are disclosed. The method includes forming a fin with a sacrificial layer on a semiconductor substrate, forming isolation regions on the semiconductor substrate and adjacent to the fin, forming a superlattice structure with first and second nanostructured layers on the sacrificial layer, forming a sacrificial structure that surrounds the superlattice structure, forming a first spacer on the superlattice structure, forming an air gap between the superlattice structure and the fin, and forming a second spacer on the fin and below the superlattice structure.

A semiconductor device is provided that includes a local passthrough interconnect structure present in a non-active device region of the device. A dielectric fill material structure is located between the local passthrough interconnect structure and a functional gate structure that is present in an active device region that is laterally adjacent to the non-active device region. The semiconductor device has reduced capacitance (and thus circuit speed is not compromised) as compared to an equivalent device in which a metal-containing sacrificial gate structure is used instead of the dielectric fill material structure.

Presented is a lateral fin static induction transistor including a semi conductive substrate, source and drain regions extending from an optional buffer layer of same or varied thickness supported by the semi conductive substrate, a semi conductive channel electrically coupling the source region to the drain region of the transistor, a portion of the semi conductive channel being a fin and having a face covered by a gated structure, thereby defining a gated channel within the semi conductive channel, the semi conductive channel further including a drift region electrically coupling the gated channel to the drain region of the transistor.

An n-type field effect transistor includes semiconductor channel members vertically stacked over a substrate, a gate dielectric layer wrapping around each of the semiconductor channel members, and a work function layer disposed over the gate dielectric layer. The work function layer wraps around each of the semiconductor channel members. The n-type field effect transistor also includes a WF isolation layer disposed over the WF layer and a gate metal fill layer disposed over the WF isolation layer. The WF isolation layer fills gaps between adjacent semiconductor channel members.