Provided is a semiconductor power device. The device includes: at least one p-type body region located on the top of an n-type drift region, a first n-type source region and a second n-type source region located within the p-type body region, a first gate structure configured to control a first current channel between the first n-type source region and the n-type drift region to be turned on or off; and a second gate structure configured to control a second current channel between the second n-type source region and the n-type drift region to be turned on or off. The second gate structure is recessed in the n-type drift region.

A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.

A semiconductor device (300A) includes a first layer (20) and a second layer (30) over the first layer. The first layer includes a logic circuit portion (23). The second layer includes a level shifter portion (24) and a pixel circuit (51). The logic circuit portion has a function of supplying a first signal for operating the level shifter portion to the level shifter portion. The level shifter portion has a function of supplying a second signal with a larger amplitude than the first signal to the pixel circuit. The logic circuit portion includes a transistor including silicon in a semiconductor layer where a channel is formed. Each of the level shifter portion and the pixel circuit includes a transistor including a metal oxide in a semiconductor layer where a channel is formed.

A semiconductor integrated circuit device includes a plurality of standard cells including a first standard cell, arranged in line in a first direction. A first buried power rail supplying a first power supply voltage is laid in a first impurity region supplied with the first power supply voltage, and extends in the first direction. A second buried power rail supplying a second power supply voltage is laid in a second impurity region supplied with the second power supply voltage, and extends in the first direction. The first standard cell includes a third buried power rail laid in the first impurity region and supplied with the second power supply voltage.

The invention of the application is the invention regarding a semiconductor device and a method for driving the semiconductor device. The semiconductor device includes first and second transistors, first to fifth switches, first to third capacitors, and a display element. The first transistor (M2) comprises a back gate, a gate of the first transistor is electrically connected to the first switch (M1), the second switch (M3) and the first capacitor (C1) are positioned between the gate of the first transistor and a source of the first transistor, the back gate of the first transistor is electrically connected to the third switch (M4), the second capacitor (C2) is positioned between the back gate of the first transistor and the source of the first transistor, the source of the first transistor is electrically connected to the fourth switch (M6) and a drain of the second transistor (M5), a gate of the second transistor is electrically connected to the fifth switch (M7), the third capacitor (C3) is positioned between the gate of the second transistor and a source of the second transistor, and the source of the second transistor is electrically connected to the display element (61).

A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The method includes providing a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein the substrate includes a topmost silicon layer and a <111> silicon layer located beneath the topmost silicon layer. Next, a trench is formed within the Group III nitride device region to expose a sub-surface of the <111> silicon layer. The trench is then partially filled with a Group III nitride base material, wherein the Group III nitride material base material has a topmost surface that is coplanar with, or below, a topmost surface of the topmost silicon layer.

Connection patterns of plural diodes include a first series connection pattern and a second series connection pattern. The first series connection pattern extends from an input terminal in the X direction. The second series connection pattern has a portion through which a current flows to approach the input terminal. The first series connection pattern includes a first diode, which is the first diode counted from the input terminal. The second series connection pattern includes a second diode, which is the last diode counted from the input terminal. The second diode is disposed separately from the first diode with some distance therebetween in the Y direction. An N-type region of the first diode and a P-type region of the second diode directly oppose each other as viewed in a planar direction.

A coil CL1 is formed on a semiconductor substrate SB via a first insulation film, a second insulation film is formed so as to cover the first insulation film and the coil CL1, and a pad PD1 is formed on the second insulation film. A laminated film LF having an opening OP1 from which the pad PD1 is partially exposed is formed on the second insulation film, and a coil CL2 is formed on the laminated insulation film. The coil CL2 is disposed above the coil CL1, and the coil CL2 and the coil CL1 are magnetically coupled to each other. The laminated film LF is composed of a silicon oxide film LF1, a silicon nitride film LF2 thereon, and a resin film LF3 thereon.

A semiconductor device includes a first circuit 1 and a second circuit 2 that are connected in series, a first terminal T1 that applies a first potential to a first power supply line DL1 of the first circuit 1, a second terminal T2 that applies a second potential to a second power supply line DL2 of the second circuit 2, a third terminal T3 that is connected to a signal transfer line of the first circuit 1, and a protection circuit that is connected to the third terminal T3, and discharges a current from the third terminal T3 to a fourth terminal T4 when a potential of the third terminal T3 becomes higher than a first threshold value. The first power supply line DL1 and the second power supply line DL2 are separated, and the fourth terminal T4 is not directly connected to the first power supply line DL1 and is electrically connected to a lead.