A semiconductor integrated circuit includes a semiconductor layer of a first conductivity type which is stacked on a support substrate with an insulating layer interposed between the semiconductor layer and the supp ort substrate, a first well region of a second conductivity type buried in an upper part of the semiconductor layer so as to be separated from the insulating layer, a second well region of the first conductivity type buried in an upper part of the first well region, and an isolation region of the first conductivity type buried in the upper part of the semiconductor layer such that the isolation region surrounds the first well region and is separated from the first well region and the insulating layer.

A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors. For example, a two turn inductor and a three turn inductor may share masks for interconnects and coils, while only masks necessary for connections between the interconnects and coils may need to be newly developed.

A semiconductor device (100) includes a substrate (11), a first TFT (10), and a second TFT (20). The first TFT includes a first semiconductor layer (12) that is supported by the substrate, a first gate electrode (14) that is formed on the first semiconductor layer and overlaps with the first semiconductor layer with a first gate insulating layer (13) interposed therebetween, a first insulating layer (16) that covers the first gate electrode, and a first source electrode (17s) and a first drain electrode (17d) that are formed on the first insulating layer and are connected to the first semiconductor layer. The second TFT includes a second gate electrode (22) that is supported by the substrate, a second semiconductor layer (25) that contains an oxide semiconductor and is formed overlapping with the second gate electrode with a second gate insulating layer (23) interposed therebetween, and a second source electrode (24s) and a second drain electrode (24d) that are formed between the second gate insulating layer and the second semiconductor layer. The first semiconductor layer and the second gate electrode are both formed from a same semiconductor film (52).

An electronic component that includes a resistive element. A Ni concentration of a resistive thin film of the resistive element at a side where there is a connection interface with a connection electrode is higher than the concentration of Ni at the side opposite to the interface.

An optical communication system, circuit, and Integrated Circuit (IC) chip are disclosed. The disclosed optical communication system includes a photodiode configured to receive light energy and convert the light energy into an electrical signal, an amplifier configured to receive the electrical signal from the photodiode and output an amplified electrical signal, and a control circuit comprising a biasing network that generates a modular logic level that scales with a bias voltage of the photodiode.

A method for producing an electrolytic capacitor according to the present disclosure is characterized by including a first step of preparing a capacitor element that includes an anode body on which a dielectric layer is formed; a second step of impregnating the capacitor element with a first treatment solution containing a first solvent and a conductive polymer; a third step of impregnating, after the second step, the capacitor element with a second treatment solution containing a second solvent; and a fourth step of impregnating, after the third step, the capacitor element with an electrolyte solution containing a third solvent, both the second solvent and the third solvent being a protic solvent.

Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device from a wafer substrate, the wafer substrate having a top-side surface with a plurality of active device die separated by saw lanes and an opposite under-side surface. The method comprises coating the under-side surface of the wafer substrate with a resilient coating, locating the position of the saw lanes from the underside surface, blade dicing trenches in the resilient material to expose under-side bulk material in the position of saw lanes, and plasma etching through the trenches to remove the exposed under-side bulk material.

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a bipolar junction transistor (BJT) is formed on the substrate, a metal-oxide semiconductor (MOS) transistor is formed on the substrate and electrically connected to the BJT, a resistor is formed on the substrate and electrically connected to the MOS transistor, a dielectric layer is formed on the substrate to cover the BJT, the MOS transistor, and the resistor, and an oxide-semiconductor field-effect transistor (OS-FET) is formed on the dielectric layer and electrically connected to the MOS transistor and the resistor.

A semiconductor device including a multiplicity of large current power elements with each power element divided into a multiplicity of divisional elements and arranged such that the power elements belonging to different power elements are arranged in a repetitive sequential order. The IC chip of the semiconductor device is formed to have output wires extending from the respective divisional elements connected to corresponding output pads without crossing other output wires. Arranged on the IC chip are output bumps in association with the respective output pads. A rewiring layer is provided having output coupling wires for connecting together the bumps that belong to the same power element and connecting them further to an external output electrode.

A multiple-unit semiconductor device (1) includes a normally-ON type first FET (11) and a normally-OFF type second FET (12) that are connected to each other in series between a first terminal and a second terminal (17 and 19). The multiple-unit semiconductor device (1) further includes a protection circuit that includes a switching element for discharge (16) connected to the second FET in parallel and a trigger circuit that is disposed between the first terminal and the second terminal (17 and 19) and causes the switching element for discharge to turn to an ON state when a surge is applied to the first terminal.