A semiconductor device, including: a plurality of unit cells formed in a semiconductor element region, each unit cell being a trench-type metal oxide semiconductor field effect transistor (MOSFET), and including a first trench; a gate runner provided in a gate runner region, which surrounds the semiconductor element region in a plan view of the semiconductor device; a ring electrode provided in a ring region, which surrounds the gate runner region in the plan view; and a termination region surrounding the ring region in the plan view. The ring region includes a second trench. At least a portion of the ring electrode is provided in the second trench.

An insulated gate bipolar transistor has: a first active area, a second active area, and a non-active area between the first active area and the second active area. Dummy trenches are disposed in the non-active area. An inter-trench region is disposed in a hole accumulation region between a first boundary gate trench and a second boundary gate trench, so as to satisfy following conditions: plural non-contact inter-trench regions are arranged in the non-active area; at least one contact inter-trench region is arranged in the non-active area; and the non-contact inter-trench regions are not adjacent to each other in the hole accumulation region.

The semiconductor device comprises a semiconductor body with a top side, a main electrode on the top side and a gate electrode. The semiconductor body comprises a drift layer of a first conductivity type, a first base region of a second conductivity type, a second base region of the first conductivity type, a first contact region of the first conductivity type and a second contact region of the second conductivity type. The second base region has a greater doping concentration than the drift layer. The first contact region adjoins the first base region and the top side. The second contact region adjoins the second base region and the top side. The main electrode is in electrical contact with the first and the second contact region. In a first lateral direction, at least a portion of the gate electrode is arranged between the first contact region and the second contact region.

The present application provides a high-voltage power semiconductor device and a method for manufacturing the same. A plurality of second resistive field plate structures is arranged in a terminal region of an epitaxial layer and extends through the epitaxial layer in a first direction to a substrate. The second resistive field plate structures are arranged concentrically and discontinuously around an active region in a first plane. The second resistive field plate structures and a third resistive field plate structure thereon form a -type combined resistive field plate structure.

A microelectronic device includes a hybrid component. The microelectronic device has a substrate including silicon semiconductor material. The hybrid component includes a silicon portion in the silicon, and a wide bandgap (WBG) structure in a silicon recess on the silicon portion of the hybrid device. The silicon recess contains a silicon recess nitride sidewall. The WBG structure includes a WBG semiconductor material having a bandgap energy greater than a bandgap energy of the silicon. The hybrid component has a first current terminal on the silicon, and a second current terminal on the WBG structure. The microelectronic device may be formed by forming the silicon portion of the hybrid component in the silicon, and subsequently forming the WBG structure in a silicon recess on the silicon.

An SGT MOSFET comprising a substrate, an epitaxial layer, a masking dielectric layer, an interlayer dielectric layer, a source lead-out contact hole, and a source conductive layer and a method for manufacturing the SGT MOSFET are provided. The epitaxial layer is on an upper surface of the substrate and comprises a cellular trench structure, a terminal lead-out structure, a source lead-out structure, a body region, and a source region. The source lead-out structure comprises a source lead-out conductive layer. The masking dielectric layer and the interlayer dielectric layer are sequentially stacked above the epitaxial layer. The source lead-out contact hole penetrates the interlayer dielectric layer and the masking dielectric layer and extends into the source lead-out conductive layer, The source conductive layer fills the source lead-out contact hole. The masking dielectric layer is formed between the interlayer dielectric layer and the epitaxial layer and masks the third dielectric layer.

A semiconductor device for high-frequency amplification includes a substrate; a first nitride semiconductor layer above the substrate; a two-dimensional electron gas layer; a second nitride semiconductor layer; and a source electrode, a drain electrode, and a gate electrode spaced apart from each other above the first nitride semiconductor layer. In a plan view, an active region with a two-dimensional electron gas layer includes a high-electron-mobility transistor and the resistor provided above the second nitride semiconductor layer. In the plan view, a non-active region includes a drain terminal and a gate terminal connected to the drain electrode or the gate electrode; and a first resistor terminal and a second resistor terminal connected to the resistor.

A semiconductor structure and method of manufacture is provided. In some embodiments, a semiconductor structure includes a semiconductor layer comprising a first uppermost surface, a lowermost surface, and a first sidewall surface extending between the uppermost surface and the lowermost surface. A gate dielectric layer is over the semiconductor layer. A first gate electrode is over a portion of the gate dielectric layer over the uppermost surface of the semiconductor layer. A first source/drain region is in the semiconductor layer under the first uppermost surface and adjacent the first gate electrode. A second source/drain region is in the semiconductor layer under the lowermost surface of the semiconductor layer.

A split gate MOSFET is provided. The split gate MOSFET may have a low capacitance between a gate electrode and a source electrode. The trench MOSFET includes a substrate; a gate trench formed on the substrate; a sidewall insulating layer formed on a sidewall of the gate trench; a source electrode surrounded by the sidewall insulating layer; a first upper electrode provided above the source electrode; a first inter-electrode insulating layer formed between the source electrode and the first upper electrode; a second upper electrode formed adjacent to a side of the first upper electrode and surrounding the first upper electrode; and an interlayer insulating layer formed on the first upper electrode and the second upper electrode.

A method for forming a semiconductor structure includes forming a pattern having first and second line features extending in a first direction on a substrate. After depositing a photoresist layer on the substrate to cover the pattern, the photoresist layer is patterned to form a cut pattern including first and second cut features exposing portions of the respective first and second line features. In a top view, at least one of the first and second cut features is asymmetrically arranged with respect to a central axis of a corresponding first or second line feature. At least one angled ion implantation is performed to enlarge the first and second cut features in at least one direction perpendicular to the first direction. The portions of the first and second line features exposed by the respective first and second cut features are then removed.