The present invention concerns a monolithically merged trenched-and-implanted Bipolar Junction Transistor (TI-BJT) with antiparallel diode and a method of manufacturing the same. Trenches are made in a collector, base, emitter stack downto the collector. The base electrode is formed on an implanted base contact region at the bottom surface of the trench. The present invention also provides for products produced by the methods of the present invention and for apparatuses used to perform the methods of the present invention.

A Light Emitting Diode (LED) light includes a bridge rectifier configured to be powered by an alternating current power source and to produce a rectified output. Control circuitry couples to the bridge rectifier and is configured to produce a shunt signal when the rectified output is less than a threshold voltage. A series connected Light Emitting Diode (LED) string includes a first group of LEDs and a second group of LEDs. A switch couples to a first side of the second group of LEDs and is controlled by the shunt signal to deactivate the second group of LEDs. The control circuitry may include a ratio metric series resistor string configured to sense a proportion of the rectified output and an inverter configured to generate the shunt signal based on the proportion of the rectified output.

A semiconductor device includes a first pad configured to receive and transmit a signal; a second pad to which a predetermined reference voltage is input; and an electrostatic protection circuit includes an emitter region electrically connected to the second pad and doped with a first conductivity-type impurity, a base region having a shape surrounding the emitter region in the first direction and the second direction and doped with a second conductivity-type impurity, different from the first conductivity-type impurity, a collector region connected to the first pad and having a shape surrounding the emitter region in the first direction and the second direction, and an impurity region disposed between the collector region and the base region and separated from the collector region and the base region by an element isolation film.

A vertical semiconductor triode includes a first layer of semiconductor material, the first layer including first and second surfaces, the first surface being in contact with a first electrode forming a Schottky contact.

The current disclosure describes a new vertical tunnel field-effect transistor (TFET). The TFET includes a source layer over a substrate. A first channel layer is formed over the source layer. A drain layer is stacked over the first channel layer with a second channel layer stacked therebetween. The drain layer and the second channel layer overlap a first surface portion of the first channel layer. A gate structure is positioned over the channel layer by a second surface portion of the channel layer and contacts a sidewall of the second channel layer.

Embodiments include a first set of fins having an emitter of a bipolar junction transistor (BJT) disposed over the first set of fins, a second set of fins having a base of the BJT disposed over the second set of fins, and a third set of fins having a collector of the BJT disposed over the third set of fins. A first gate structure is disposed over the first set of fins adjacent to the emitter. A second gate structure is disposed over the second set of fins adjacent to the base. A third gate structure is disposed over the third set of fins adjacent to the collector. The first gate structure, second gate structure, and third gate structure are physically and electrically separated.

Embodiments include a first set of fins having an emitter of a bipolar junction transistor (BJT) disposed over the first set of fins, a second set of fins having a base of the BJT disposed over the second set of fins, and a third set of fins having a collector of the BJT disposed over the third set of fins. A first gate structure is disposed over the first set of fins adjacent to the emitter. A second gate structure is disposed over the second set of fins adjacent to the base. A third gate structure is disposed over the third set of fins adjacent to the collector. The first gate structure, second gate structure, and third gate structure are physically and electrically separated.

Described herein are various amorphous metal thin film transistors. Embodiments of such transistors include an amorphous metal gate electrode and a channel conductor formed on a non-conducting substrate. Further embodiments of such transistors include an amorphous metal source electrode, an amorphous metal drain electrode, and a channel conductor formed on a non-conducting substrate. Methods of forming such transistors are also described.

A tunneling transistor includes a gate, an insulating layer placed on the gate, a carbon nanotube being semiconducting, a film-like structure, a source electrode, and a drain electrode. The carbon nanotube is placed on a surface of the insulating layer away from the gate. The film-like structure covers a portion of the carbon nanotube, and the film-like structure is a molybdenum disulfide film or a tungsten disulfide film. The source electrode is electrically connected to the film-like structure. The drain electrode is electrically connected to the carbon nanotube.

Electrostatic discharge (ESD) protection is provided in circuits which use of a tunneling field effect transistor (TFET) or an impact ionization MOSFET (IMOS). These circuits are supported in silicon on insulator (SOI) and bulk substrate configurations to function as protection diodes, supply clamps, failsafe circuits and cutter cells. Implementations with parasitic bipolar devices provide additional parallel discharge paths.