An integrated circuit (IC) structure is described. The IC structure includes a substrate having an active/passive device in the substrate. The IC structure also includes a terminal of the active/passive device in the substrate. The IC structure further includes a floating contact field plate above the terminal. The IC structure also includes a dielectric layer between the floating contact field plate and the terminal of the active/passive device.

A semiconductor device includes a voltage input circuit node and a ground voltage node. A first transistor is coupled between the voltage input circuit node and the ground voltage node. A triggering circuit is coupled between the voltage input circuit node and the ground voltage node in parallel with the first transistor. The triggering circuit includes a trigger diode. An output of the triggering circuit is coupled to a control terminal of the first transistor. A load is powered by coupling the load between the voltage input circuit node and the ground voltage node.

The disclosed subject matter relates generally to an inductor structure integrated in a semiconductor device formed from bonded wafers, in which the semiconductor device has a three-dimensional inductor structure aligned vertically between two integrated circuit (IC) components. The inductor structure has a first metal level and a second metal level, the first metal level being in a different wafer from the second metal level.

Embodiments of the disclosure provide a bipolar transistor structure with a ferroelectric material. A structure of the disclosure may include a base over a substrate. The base includes a first portion laterally between an emitter and a collector, and a second portion over the first portion. A ferroelectric spacer is adjacent the second portion of the base. Other structures include a ferroelectric layer over a back gate terminal of a substrate. A base is on the ferroelectric layer. The base includes a first portion laterally between an emitter and a collector, and a second portion over the first portion.

A semiconductor device includes a voltage input circuit node and a ground voltage node. A first transistor is coupled between the voltage input circuit node and the ground voltage node. A triggering circuit is coupled between the voltage input circuit node and the ground voltage node in parallel with the first transistor. The triggering circuit includes a trigger diode. An output of the triggering circuit is coupled to a control terminal of the first transistor. A load is powered by coupling the load between the voltage input circuit node and the ground voltage node.

A silicon carbide power semiconductor device having a folded channel area, and a manufacturing method therefor are disclosed. The power semiconductor device comprises a gate protection circuit unit arranged between a source metal and a gate electrode, wherein the gate protection circuit unit comprises: an embedded diode which is formed such that a first conductive ion injection area and a second conductive ion injection area are alternately connected in multiple stages to a polysilicon layer insulated by an insulation film layer formed on the upper side surface of a semiconductor substrate, and which has one side end electrically connected to the source metal and another side end electrically connected to the gate electrode; and one or more floating metal layers for shorting the first conductive ion injection area and the second conductive ion injection area, which are adjacent to each other in the embedded diode.

The invention provides a transistor outline (TO) packaging structure, which comprises a lower substrate, the lower substrate comprises a lower ceramic substrate, a lower conductive layer and a lower heat dissipation layer, an upper substrate, the upper substrate comprises an upper ceramic substrate, an upper conductive layer and an upper heat dissipation layer, a chip located between the lower substrate and the upper substrate, a molding material layer covering the chip and covering part of the lower substrate and the upper substrate, and a metal tab comprising an pin hole, wherein when from a cross-sectional view, a top surface of the upper substrate, a top surface of the metal tab, and a sidewall of the molding material layer form a stepped structure.

An electrostatic discharge semiconductor device is disclosed and comprises: a first well region of a first doping type, extending from the surface of an epitaxial layer to the surface of the substrate; a second well region and a third well region of a second doping type; a fourth well region of the second doping type; a fifth well region and a sixth well region have a first doping type; a first injection region and a second injection region, spaced apart in each well region. The second injection region in the second and third well regions is connected to a cathode, and the first and second injection regions in the fourth well region are connected to an anode. The electrostatic discharge semiconductor device enhances its electrostatic protection capability by adjusting the avalanche breakdown voltage between the floating fifth and sixth well regions and the triggering voltage of the device.

An electrostatic discharge semiconductor device and a manufacturing method thereof are disclosed. The electrostatic discharge semiconductor device includes: a substrate, an epitaxial layer and a first well region; a second well region and a third well region located on sides of the first well region respectively; a fourth well region extending in the first well region; fifth and sixth well regions on sides of the fourth well region; a first injection region and a second injection region. The second injection region in the second well region and third well region, and the first injection region in the fifth well region and sixth well region are connected to a cathode, and all injection regions in the fourth well region are connected to an anode, to form a lateral triode current discharge path, which increases the holding voltage and adjusts the avalanche breakdown voltage and trigger voltage, and enhances electrostatic protection capability.

A power semiconductor device includes a mounting base; a power chip fixed on the mounting base; a bond wire electrically connecting the power chip to a circuit pattern on the mounting base; a columnar electrode seat disposed on the mounting base; a plastic housing encapsulating an upper surface of the mounting base, the power chip, the bond wire, and the columnar electrode seat. The plastic housing includes a through hole aligned with the columnar electrode seat (e.g. pin holders). An insulating ring is embedded on the surface of the plastic housing and surrounds the through hole. A metal pin is inserted into the through hole and fixed on the columnar electrode seat. The insulating ring and the plastic housing are made of different materials.