Double patterning techniques described herein may reduce corner rounding, etch loading, and/or other defects that might otherwise arise during formation of a deep trench isolation (DTI) structure in a pixel array. The double patterning techniques include forming a first set of trenches in a first direction and forming a second set of trenches in a second direction in a plurality of patterning operations such that minimal to no etch loading and/or corner rounding is present at and/or near the intersections of the first set of trenches and the second set of trenches.

Disclosed is an image sensor including first to fourth, fifth to eighth, ninth to 12.sup.th and 13.sup.th to 16.sup.th unit pixel circuits, a first readout line connected to the first and ninth unit pixel circuits, a second readout line connected to the fifth and 13.sup.th unit pixel circuits, a third readout line connected to the second and 10.sup.th unit pixel circuits, a fourth readout line connected to the sixth and 14.sup.th unit pixel circuits, a fifth readout line connected to the third and 11.sup.th unit pixel circuits, a sixth readout line connected to the seventh and 15.sup.th unit pixel circuits, a seventh readout line connected to the fourth and 12.sup.th unit pixel circuits, an eighth readout line connected to the eighth and 16.sup.th unit pixel circuits, first to fourth readout circuits, and a path selector connecting the unit pixel circuits to the readout circuits via the readout lines.

A photoelectric packaging structure, and a preparation method of the photoelectric packaging structure, and a camera module having the photoelectric packaging structure are provided. The photoelectric packaging structure includes a substrate module and a photosensitive chip. The substrate module includes a substrate, and the substrate module defines a plurality of channels. The photosensitive chip is located on the substrate, and includes a photosensitive area and a non-photosensitive area connected to the photosensitive area. Two ends of each of the channels extend to the substrate and the non-photosensitive area, respectively. A conductive layer is formed on an inner wall of each of the channels to form a hollow conductive channel. The hollow conductive channel is electrically connected to the substrate and the non-photosensitive area.

A semiconductor device, a manufacturing method therefor, and an electronic apparatus that reduces a parasitic capacitance generated between an internal electrode and a board silicon to suppress waveform distortion and signal delay of high-frequency signals, thereby enabling a high-speed operation. A configuration to include: a board silicon; a silicon oxide film stacked on the board silicon; an inter-wiring-layer film having an internal electrode stacked on the silicon oxide film; a through-hole forming a stepped hole with a larger-diameter hole extending from the board silicon to the silicon oxide film and a smaller-diameter hole extending from the silicon oxide film to the internal electrode; an interlayer dielectric film stacked on a circumferential side surface of the larger-diameter hole and the board silicon; and a redistribution layer on an inner peripheral surface of the through-hole and the interlayer dielectric film and connected to the internal electrode.

A voltage to be applied to a charge holding section to which charges generated by a plurality of photoelectric conversion sections are transferred is adjusted. An imaging element includes a plurality of photoelectric conversion sections, a charge holding section, a plurality of charge transfer sections, an image signal generation section, and a plurality of capacitive coupling wirings. The photoelectric conversion section performs photoelectric conversion of incident light to generate a charge. The charge holding section holds the generated charge. The charge transfer section is arranged for each photoelectric conversion section and transfers the generated charge to the charge holding section. The image signal generation section generates an image signal corresponding to the held electric charge. The capacitive coupling wirings are capacitively coupled to the charge holding section, and are individually applied with an adjustment signal for adjusting the potential of the charge holding section.

A potential of a charge retaining unit that retains a charge generated by photoelectric conversion is adjusted. An imaging element includes a photoelectric conversion unit, a charge retaining unit, a charge transfer unit, a reset unit, an image signal generating unit that generates an image signal, capacitive coupling wiring, and a potential adjustment unit. The photoelectric conversion unit is formed on a semiconductor substrate and performs photoelectric conversion of incident light. The charge retaining unit retains a charge generated by photoelectric conversion. The charge transfer unit transfers the charge generated by photoelectric conversion to the charge retaining unit. The reset unit discharges the charge retained in the charge retaining unit. The image signal generating unit generates an image signal on the basis of the charge retained in the charge retaining unit. The capacitive coupling wiring is different from wiring that transmits control signals of the charge transfer unit, the reset unit, and the image signal generating unit and wiring that transmits a generated image signal and is capacitively coupled to the charge retaining unit. The potential adjustment unit applies an adjustment signal for adjusting the potential of the charge retaining unit via the capacitive coupling wiring.

Long wavelength polarization sensitive image sensor devices and methods are provided. The image sensor includes pixels that each include a plurality of sub-pixels. At least some of the sub-pixels within each pixel are associated with a grid structure. Each grid structure includes two or more linear grid elements that are parallel to one another. The grid elements are disposed directly on a light incident surface of a sensor substrate in which the sub-pixels are formed, and are electrically floating. The sub-pixels can be formed as photodiodes in a silicon or other semiconductor substrate. Infrared light incident on the pixels results in the heating of the grid elements, and in particular of grid elements oriented in a direction that is parallel to a polarization of the incident light, which in turn generates a current in associated a sub-pixels. A polarization state and intensity of the incident light can be determined.

An image sensor comprises at least two vertically stacked photo-sensitive devices wherein each respective photo-sensitive device comprises a stack of a top electrode, a first charge transport layer and an active layer. Each respective stack generates electrical charges in response to a corresponding predefined range of wavelengths of light incident on the image sensor. Each photo-sensitive device further comprises a second charge transport layer having a first portion, vertically aligned underneath the active layer, and a second portion, transfer region, protruding laterally to extend beyond the active layer. A dielectric layer separates the first portion from a bottom electrode providing a voltage for depleting the first portion, and the transfer region from a transfer gate providing a voltage for transferring the generated electrical charge to a floating electrical connection, shared by all stacked photo-sensitive devices. The floating electrical connection couples to a read-out-circuitry.

A PIN diode detector includes a substrate. The PIN diode detector further includes a plurality of PIN diode wells in a pixel region, wherein each of the plurality of PIN diode wells has a first dopant type. The PIN diode detector further includes a connecting ring well and a plurality of floating ring wells in a peripheral region, wherein the connecting ring well and plurality of floating ring wells have the first dopant type. The PIN diode detector further includes a field stop ring well surrounding the plurality of floating ring wells, wherein the field stop ring well has a second dopant type opposite the first dopant type. The PIN diode detector further includes a blanket doped region. The blanket doped region extends continuously through an entirety of the pixel region and an entirety of the peripheral region, and the blanket doped region has the second dopant type.

An electronic device including a substrate, a silicon transistor disposed on the substrate, an oxide transistor disposed on the substrate and electrically connected to the silicon transistor, and a sensor configured to receive a light and output a signal. The silicon transistor and the oxide transistor are operated corresponding to the signal.