The present disclosure provides a display backplane and a preparation method therefor, and a display apparatus. The display backplane includes a plurality of display units, at least one display unit includes a pixel area and a light transmitting area, the pixel area is configured to perform image display and the light transmitting area is configured to transmit light; and in a plane perpendicular to the display backplane, the light transmitting area includes a substrate and a light transmitting structure layer arranged on the substrate, and the light transmitting structure layer is provided with light transmitting holes.

In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.

The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.

There is provided a semiconductor device including: a semiconductor substrate; a gate insulating film provided on the semiconductor substrate; a gate electrode layer that is provided on the gate insulating film and contains impurity ions; and source or drain regions that are provided on the semiconductor substrate on both sides of the gate electrode layer and contain conductive impurities, in which a concentration of the impurity ions in the gate electrode layer is higher than concentrations of the conductive impurities in the source or drain regions.

A variable capacitor is formed from a pair of electrodes and a dielectric interposed between the electrodes over a substrate, and an external input is detected by changing capacitance of the variable capacitor by a physical or electrical force. Specifically, a variable capacitor and a sense amplifier are provided over the same substrate, and the sense amplifier reads the change of capacitance of the variable capacitor and transmits a signal in accordance with the input to a control circuit.

The present disclosure discloses a panel structure of flat displays and the manufacturing method thereof. The panel structure includes a first signal line, a second signal line, a transparent conductive film, and a scanning line. The transparent conductive film includes a first branch, a second branch, and a third branch. A first end of the first branch and a first end of the second branch are connected by a predetermined first angle, and a second end of the second branch and a first end of the third branch are connected by a predetermined second angle. The first branch, the second branch, and the third branch form the arch-shaped frame. The first signal line connects to the second end of the first branch, and the second signal line connects to the second end of the third branch. The scanning line passes through the arch-shaped frame along a first direction.

The present invention provides a display device and a manufacturing method thereof that can simplify manufacturing steps and enhance efficiency in the use of materials, and further, a manufacturing method that can enhance adhesiveness of a pattern. One feature of the invention is that at least one or more patterns needed for manufacturing a display panel, such as a conductive layer forming a wiring or an electrode or a mask for forming a desired pattern is/are formed by a method capable of selectively forming a pattern, thereby manufacturing a display panel.

The present invention provides a display substrate and a manufacturing method thereof. The display substrate of the present invention comprises a first structure and a second structure; wherein, the second structure is provided with a lap portion disposed on the first structure and a main body portion connected with the lap portion and outside the first structure; the first structure has a thinned region connected to an edge thereof, and a thickness of the first structure in the thinned region is smaller than that outside the thinned region; and at least part of the lap portion is located on the thinned region, and at least part of the main body portion outside the thinned region is in direct connection with the part of the lap portion on the thinned region.

An SOI substrate evaluating method includes: forming a device onto a measuring SOI substrate, and previously determining a relationship between an interface state density and a leakage power upon application of radio-frequency thereon, or converting the interface state density to a resistance followed by previously determining a relationship between the converted resistance and the leakage power; measuring an interface state density of the evaluation target SOI substrate to determine the interface state density or a resistance converted from the interface state density; evaluating a leakage power of the evaluation target SOI substrate from the measured interface state density of the evaluation target SOI substrate on the basis of the determined relationship between the interface state density and the leakage power, or from a resistance converted from the measured interface state density of the evaluation target SOI substrate on the basis of the determined relationship between the resistance and leakage power.

Provided are space-efficient capacitors that have a higher quality factor than conventional designs and improve coupling of electrical energy from a through-glass via (TGV) to a dielectric. For example, provided is a TGV having a non-rectangular cross-section, where one end of the TGV is coupled to a first metal plate. A dielectric material is formed on the first metal plate. A second metal plate is formed on the dielectric material in a manner that overlaps at least a portion of the first metal plate to form at least one overlapped region of the dielectric material. At least a part of the perimeter of the overlapped region is non-planar. The overlapped region can be formed in a shape of a closed ring, in a plurality of portions of a ring shape, in substantially a quarter of a ring shape, and/or in substantially a half of a ring shape.