The present inventive concept relates to a spin qubit transistor (100) comprising a base layer (102), a first qubit comprising, a first computing semiconductor island (106) and a first readout semiconductor island (108) arranged with a distance in the range of 3-10 nm therebetween, a second qubit comprising, a second computing semiconductor island (110) and a second readout semiconductor island (112) arranged with a distance in the range of 3-10 nm therebetween, wherein each of said semiconductor islands has a size causing each of said semiconductor islands to exhibit 3-dimensional quantum confinement of a single electron hole, and wherein each of said semiconductor islands forms a semiconductor heterojunction with the base layer. Each of the semiconductor islands has a corresponding gate (G1-G4), for modulation of the computing islands or readout of the readout islands. Said first computing semiconductor island and said second computing semiconductor island are configured to have a unique resonance frequency respectively. A control electrode arrangement (B) between the computing and the readout islands controls the coupling between the qubits. The present inventive concept further comprises a method for forming a spin qubit transistor and a quantum computer comprising at least one spin qubit transistor.

Disclosed are heterostructures that deploy one or more ultra-clean layers of van der Waals materials (VdW heterostructures). Further disclosed are techniques of fabricating VdW heterostructures that include patterning a conducting layer positioned on a substrate, separating, using a curved lifting surface, the patterned conducting layer from the substrate, and transferring the patterned conducting layer to a receiving stack of one or more layers while removing residual contaminants.

A semiconductor device includes a field effect transistor (FET) with at least one Gate-All-Around (GAA) channel. A first conductive ferromagnetic Source/Drain contact is electrically connected with a first portion of the GAA channel. A second conductive ferromagnetic Source/Drain contact is electrically connected with a second portion of the GAA channel. A remanent magnetization of the first conductive ferromagnetic contact is oriented in a direction opposite to a remanent magnetization of the second conductive ferromagnetic contact.

A semiconductor spintronic device is disclosed, which includes a substrate, a first ferromagnetic contact layer and a second ferromagnetic contact layer disposed on the substrate, and a semiconductor nanomembrane, disposed between the first ferromagnetic contact layer and the second ferromagnetic contact layer. The semiconductor spintronic device can include a screw dislocation throughout the thickness of the semiconductor nanomembrane layers. Methods of fabricating and operating a semiconductor spintronic device are also disclosed.

Quantum dot devices and related methods and systems that use semiconductor nanoribbons arranged in a grid where a plurality of first nanoribbons, substantially parallel to one another, intersect a plurality of second nanoribbons, also substantially parallel to one another but at an angle with respect to the first nanoribbons, are disclosed. Different gates at least partially wrap around individual portions of the first and second nanoribbons, and at least some of the gates are provided at intersections of the first and second nanoribbons. Unlike previous approaches to quantum dot formation and manipulation, nanoribbon-based quantum dot devices provide strong spatial localization of the quantum dots, good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices.

The invention relates to a method for calibrating a two-level spin quantum system coupled to a microwave cavity by a symmetric magnetic field and an antisymmetric magnetic field in the form of a double quantum dot comprising a left dot and a right dot, which system is subjected to a bias voltage, the method being characterized by the following steps: setting the bias voltage () to zero volts; determining a wave function p of each of the quantum dots; calculating and/or setting the antisymmetric das and symmetric as magnetic coupling constants, calculating and/or setting the tunnel coupling constant, and/or the symmetric magnetic coupling constant s and/or the antisymmetric magnetic coupling constant as.

The present invention relates to a spin-orbit torque magnetic device and a method of manufacturing the same. The spin-orbit torque magnetic device according to one embodiment may include a first heavy metal layer, a ferromagnetic layer formed on the first heavy metal layer, a second heavy metal layer formed on the ferromagnetic layer, and a gate oxide layer formed on the second heavy metal layer. Here, in the second heavy metal layer, when a gate voltage of a preset magnitude is applied to the gate oxide layer, the strength of spin-orbit interaction may be controlled.

This field effect transistor has: a substrate having a (111) surface, the substrate comprising a group IV semiconductor doped with a first electroconductivity type; a core-shell nanowire including a core nanowire connected to the (111) surface of the substrate, the core nanowire comprising a group III-V compound semiconductor doped with a second electroconductivity type different from the first electroconductivity type, and a shell layer disposed so as to cover the core nanowire, the shell layer comprising a group III-V compound semiconductor doped with the first electroconductivity type; a first electrode electrically connected to the shell layer; a second electrode electrically connected to the substrate; and a gate electrode for inducing a field at the joining interface between the substrate and the core nanowire and at the shell layer.

A spin qubit quantum device includes a semiconductor portion having a first region disposed between two second regions; a first control gate disposed in direct contact with the first region and configured to control a minimum potential energy level in the first region, and disposed in direct contact with a first face of the semiconductor portion; and second electrostatic control gates, each disposed in direct contact with one of the second regions and configured to control a maximum potential energy level in one of the second regions, and disposed in direct contact with a second face, opposite to the first face, of the semiconductor portion, The first gate is not aligned with the second gates.

A thin film transistor, a thin film transistor substrate, a method of manufacturing a thin film transistor and a display apparatus including the thin film transistor are provided. The thin film transistor includes a base substrate, an active material layer on the base substrate, and a gate electrode spaced apart from the active material layer and overlapping at least a portion of the active material layer. The active material layer includes a channel portion overlapping the gate electrode, a source connection portion contacting one side of the channel portion, a drain connection portion contacting the other side of the channel portion and an insulating portion contacting at least one of the source connection portion and the drain connection portion. Further, the channel portion, the source connection portion, the drain connection portion, and the insulating portion are disposed on a same layer.