A semiconductor device includes a substrate, a sensing device, and a transistor. The sensing device includes a dielectric layer, a sensing pad, a first sensing electrode, and a second sensing electrode. The dielectric layer is over the substrate. The sensing pad is over and in contact with the dielectric layer. The first sensing electrode and the second sensing electrode are over and in contact with the dielectric layer. The first sensing electrode and the second sensing electrode surround the sensing pad, and a distance between the first sensing electrode and the second sensing electrode is greater than a distance between the sensing pad and the first sensing electrode. The transistor is over the substrate. A gate of the transistor is connected to the sensing pad.

Disclosed is a spin light emitting device based on two-dimensional material. The light emitting device comprises: a two-dimensional structure configured to emit circularly polarized light in response to spin-polarized carrier injection, wherein the two-dimensional structure is a two-dimensional Van der Waals heterostructure; a spin injector configured to inject spin-polarized carriers into the two-dimensional Van der Waals heterostructure, wherein the light emitted by the two-dimensional structure has a circular polarization state determined by the magnetization state of the spin injector; and a magnetization controller configured to change the magnetization state of the spin injector. The spin-based light emitting device emits circularly polarized light or single photons on the basis of two-dimensional material at room temperature without introducing a magnetic field, and has the capability of electrical control.

A tunneling field effect transistor having a buried drain structure is provided. The tunneling field effect transistor comprises a semiconductor pattern disposed on a substrate and including a thin part at one end, a thick part at the other end, and a step between the thin part and the thick part. A drain electrode is disposed on the thin part, a source electrode is disposed on the thick part, and a gate electrode is disposed on the thick part between the drain electrode and the source electrode. A gate insulating layer is disposed between the semiconductor pattern and the gate electrode and between a sidewall of the step of the semiconductor pattern and the drain electrode. The semiconductor pattern has a drain region of a first conductivity type induced by generation of a charge plasma of the first conductivity type in an area adjacent to the drain electrode, and a source region of a second conductivity type induced by generation of a charge plasma of the second conductivity type in an area adjacent to the source electrode, and a channel region between the source region and the drain region. A thickness of the drain electrode is lower than a height of the step of the semiconductor pattern.

An ion trap device in which a return line portion and one or more signal line portions, for driving an electrode of the ion trap device, are configured to run alongside one another in close proximity for a majority of the length of the return line portion.

A qubit device includes first and second linear qubit arrays. Each qubit array includes a semiconductor substrate, control gates configured to define a single row of quantum dots along the substrate, and nanomagnets distributed along the row of quantum dots such that a nanomagnet is arranged at every other pair of quantum dots of the row of quantum dots. Each nanomagnet has an out-of-plane magnetization with respect to the substrate, where the rows of the first and second arrays extend in a common row direction and are separated along a direction transverse to the row direction. The qubit device further includes superconducting resonators connecting pairs of quantum dots between the first and second arrays. Each pair of quantum dots in the first array is configured to couple with a superconducting resonator of the first set to connect with a different pair of quantum dots of the second array.

A method for making a qubit device comprising a chiral nanocrystal includes forming a gate electrode on a non-conducting substrate, forming an insulating layer over the back gate electrode, immobilizing a bottom face of a semiconductor nanocrystal onto the insulating layer, and placing two or more electrodes on, or in apposition to, a top face of the semiconductor nanocrystal.

A fin-based tunneling filed field effect transistor (TFET) includes a control gate structure and an assisting gate structure adjacent to the control gate structure. The assisting gate structure is disposed between the control gate structure and a source/drain region of the fin-based TFET. When a voltage is applied to the assisting gate structure, the assisting gate structure causes the valence band of the fin-based TFET to be raised near the junction between the source/drain region and a channel region in a semiconductor layer under the assisting gate structure. This reduces the tunneling distance between the source/drain region and the channel region, which allows for a lesser threshold voltage to be used for the control gate structure than without the assisting gate structure.

A device includes depletion gates, an accumulation gate, and a conductive resonator. The depletion gates extend lengthwise along a first direction over a substrate. The accumulation gate includes a conductive bridge extending lengthwise along a second direction across the depletion gates and spaced apart from the depletion gates. The conductive resonator is over the accumulation gate. The conductive resonator includes a conductive bridge extending lengthwise along the second direction across the depletion gates and spaced apart from the accumulation gate.

A quantum device comprising an array of quantum dots is disclosed. The quantum device comprises a silicon layer in which quantum dots (201) can be induced by respective gates; gates of the inducible quantum dots (201) for controlling an electrical potential that define the induced quantum dots (201); and integrated circuit elements (204), in particular comprising floating gate field effect transistors, for controlling the voltages of the respective gates, the integrated circuit elements (204) having non-volatile resistance value, RF, which are tunable. The integrated circuit elements (204) have input voltages (Vin) and an output voltages (Vout), wherein the output voltages are dependent on the input voltages and the non-volatile resistance values RF of the different integrated circuit elements. The integrated circuit elements (204) are electrically connected such that their respective output voltages are applied to the gates of the respective inducible quantum dot (201). The gates of the individual quantum dots can thus be addressed using a single input voltage.

A semiconductor structure includes a dielectric layer, a sensing pad, and first, second, and third sensing electrodes. The dielectric layer is disposed over a substrate. The sensing pad is disposed over the dielectric layer. The first, second, and third sensing electrodes are disposed over the dielectric layer, wherein, in a top view, the first, second, and third sensing electrodes are spaced apart from each other and collectively surround the sensing pad.