A transistor with improved low-frequency noise characteristics is disclosed. Phase complexing channel layer having quantum dots distributed within an amorphous matrix is formed, and a surface stabilization layer is formed in contact with the phase complexing channel layer. The surface stabilization layer has a repeating structure of an inorganic insulating layer and an organic shielding layer. Since the quantum dots of the phase complexing channel layer are in a quantized state, carriers trapped in the quantum dots are limited. Even if current is generated at the phase complexing channel layer by the drain-source voltage, the carriers trapped at the quantum dots are maintained at a constant level. Accordingly, the drain-source current is constant even when the gate voltage increases, and the noise component of the gate voltage is not reflected in the drain current.

The present disclosure provides a quantum processing device comprising: one or more functional nanowires, each functional nanowire connected to at least one of a source and a drain; a sensing nanowire spaced from the one or more functional nanowires and connected to at least one of a source and a drain; one or more gate electrodes capacitively coupled with each of the one or more functional nanowires; one or more electrodes capacitively coupled with the sensing nanowire; and a floating coupler positioned between and electrostatically coupling the one or more functional nanowires and the sensing nanowire; and a controller connected to the one or more gates of the sensing nanowire and the one or more gates of the one or more functional nanowires.

A three-dimensional (3D) topological insulator (Tl), configured with a surface channel for conducting spin polarized electron flow, and piezoelectric element that strains the 3D Tl, responsive to an input voltage, producing stress in the surface channel according to a voltage-to-stress characteristic (VTSC). A spin polarizer and spin analyzer act as source and drain and produce an electric field through the surface channel when a voltage is applied between the source and drain, the spin polarizer injects spin polarized electrons to flow through the surface channel and arrive at the spin analyzer as arrival electrons. The surface channel has a stress-to-rotation characteristic (STRC) that, responsive to the stress, rotates the spin polarization such that the arrival electrons have a rotated plane of polarization, at a rotation angle.

A FET with a multi-value switching function comprises a source region, a channel region, a drain region, a gate dielectric layer, a substrate layer, a gate-oxide inducer layer, a metal layer and a spacer layer. The channel region is an undoped channel region, the drain region is an undoped drain region. The metal layer comprises first to third metal blocks which are arranged at intervals from left to right, the distance between the first metal block and the second metal block is 12 nm, the distance between the second metal block and the third metal block is 10 nm, the first metal block is a main control gate of the FET, the second metal block and the third metal block are two inducer gates of the FET, and the spacer layer is used for isolating the first metal block from the second metal block and the third metal block.

A power semiconductor circuit includes: a power semiconductor element having a gate electrode configured to actuate the power semiconductor element, a collector electrode, and an emitter electrode electrically connected to a first emitter terminal; and a temperature sensor having a first measurement point with a measurement terminal and a second measurement point electrically connected to the emitter electrode, so that a voltage which drops over the temperature sensor is measurable between the measurement terminal and the first emitter terminal for the temperature measurement. Corresponding methods for determining a temperature of a power semiconductor element and for determining a sign of a load current in a bridge circuit are also described.

A fin field-effect transistor device with hybrid conduction mechanism, including a fin field-effect transistor, a second source region, and a second drain region; the fin field-effect transistor includes a substrate, a fin channel region, a first source region, and a first drain region; the height of the second source region is not lower than the height of the substrate between the first source region and the first drain region; the first source region the first drain region and the second drain region are doped with first ions; the second source region is formed between the substrate and the first source region, the second drain region is formed between the substrate and the first drain region, the second source region is doped with second ions. This scheme can realize hybrid conduction of fin channel diffusion drift current and bottom channel band-to-band tunneling current, thus obtaining better ultra-steep switching characteristics.

A quantum computing device includes an optical resonator having a resonant wavelength band. A crystalline material including a crystal defect is contained within the optical resonator. The crystal defect has a ground state and an excited state, which has an emission wavelength in the resonant wavelength band. A source electrode and a drain electrode are disposed on opposing sides of the crystal defect and configured to apply a first electric field in the crystalline material along a longitudinal axis. A gate electrode is disposed in proximity to the crystal defect and configured to apply to the crystalline material a second electric field transverse to the longitudinal axis. Control circuitry is configured to apply a first voltage between the source and drain electrodes to control a charge state of the crystal defect and to apply a second voltage to the gate electrode to tune the emission wavelength.

A quantum device is described that includes a substrate with a layered structure, e.g. heterostructure, forming a quantum well layer. A doped region is connected to the layered structure for exchanging charge carriers with the quantum well layer. A patterned layer of electrically conductive material forms a set of gates including an accumulation gate. The accumulation gate comprises an accumulation pad configured to accumulate a two-dimensional charge carrier gas (2DCCG) in an active region of the quantum well layer connected there below to the doped region. At least part of an electric pathway between the accumulation pad and a connection pad is narrowed to form a nanoscale constriction for cutting off the active region of the quantum well layer.

There is provided a method for performing one or more quantum operations on a quantum processor. Wherein the quantum processor comprises a plurality of quantum dots in a semiconductor substrate and at least a subset of the quantum dots being multi-dopant quantum dots. Further each multi-dopant quantum dot comprises two or more dopant atoms and at least one of the plurality of quantum dots confining an unpaired electron/hole. The method comprises performing the one or more quantum operations on the quantum processor using one or more operation modes including: using the spin of the unpaired electron/hole of a quantum dot as a data qubit; using a multi-dopant quantum dot as an error corrected logical qubit; using at least one nuclear spin of a dopant atom of a multi-dopant quantum dot as a data qubit; or using the spin of the unpaired electron/hole and at least one nuclear spin of a dopant atom of a multi-dopant quantum dot as data qubits.

A quantum computing method includes providing at least one resonator-coupled quantum emitter configured to function as an entangling gate, receiving a plurality of graph states, at least some of the plurality of graph states representing a relationship between qubits therein, and wherein at least one of the qubits in at least two of the plurality of graph states is a photonic qubit, selecting the at least one photonic qubit from each of the at least two of the plurality of graph sates, interacting the selected qubits with the at least one resonator-coupled quantum emitter, and disentangling the at least one resonator-coupled quantum emitter from the selected qubits.