Various integrated circuit transistor device structures that implement nanosheet fin transistors are disclosed. Layouts for the transistor device structures include active cells with dummy cells positioned between active cells. The active cells and dummy cells may include nanosheet fin regions that have different widths. In certain instances, the transitions between different nanosheet fin regions widths (e.g., jogs in the widths) are positioned inside the dummy cells rather than at interfaces between the dummy cells and the active cells. Placing the jogs in widths inside the dummy cells reduces mechanical stresses between active cells and dummy cells and allows for design changes in the size of active transistors during a manufacturing process.

A composite semiconductor substrate includes a bulk semiconductor substrate and a first well region. The bulk semiconductor substrate has an original semiconductor surface and with a first doping type. The first well region is in the bulk semiconductor substrate with a second doping type, wherein the first doping type is different from the second doping type. There is no PN junction between the bulk semiconductor substrate and the first well region.

The present disclosure provides a transistor, a method for configuring the same, an electrostatic discharge (ESD) protection circuit, and an electronic device for ESD protection. The transistor comprises a P-type well, a body terminal region, a source region, and a metal silicide layer. The body terminal region and the source region are disposed within the P-type well. The body terminal region is adjacent to the source region. The metal silicide layer is disposed on surfaces of the body terminal region and the source region, and electrically connected to the body terminal region and the source region separately. A metal and contact structures are provided on the metal silicide layer to adjust the resistance between the emitter of the parasitic bipolar transistor of the transistor and the body terminal region or between the base of the parasitic bipolar transistor and the source region, for ESD protection.

Provided are a display panel and a display apparatus, the display panel includes a substrate and a drive circuit layer, wherein the drive circuit layer includes a pixel circuit (P) arranged in an array, a plurality of first scan signal lines (G1) and a plurality of second scan signal lines (G2). The drive circuit layer includes a plurality of first discharge structures (E1) and/or a plurality of second discharge structures (E2). At least one first discharge structure (E1) is electrically connected to a first scan signal line (G1) and a second scan signal line (G2) respectively, and the first scan signal line (G1) and the second scan signal line (G2) electrically connected to the first discharge structure (E1) are electrically connected to the same row of pixel circuit.

An example semiconductor die includes a set of circuit components, a first interconnect circuit, and a second interconnect circuit, all arranged on a substrate. The first interconnect circuit is configured for a first interface type and includes one or more first signaling components and a first connection interface. The second interconnect circuit includes second signaling component(s) and a second connection interface, and is configured for a second interface type having requirement(s) that differ from requirement(s) of the first interface type. When the first interface type is selected, the first connection interface is electrically coupled to the first signaling components, and the second connection interface is electrically isolated from the second signaling components. When the second interface type is selected, the first connection interface is electrically isolated from the first signaling components, and the second connection interface is electrically coupled to the second signaling components.

An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0.

Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. The semiconductor device includes a semiconductor body, a device region, and the deep trench isolation structure. The deep trench isolation structure is configured to electrically isolate the device region from other device regions that extend within the semiconductor body. The deep trench isolation structure includes an isolation trench, a dielectric material that extends within the isolation trench, a first semiconducting region, and a second semiconducting region. The methods include methods of operating an integrated circuit device that includes a plurality of semiconductor devices that include the disclosed deep trench isolation structures.

Light emitting devices and methods of integrating micro LED devices into light emitting device are described. In an embodiment a light emitting device includes a reflective bank structure within a bank layer, and a conductive line atop the bank layer and elevated above the reflective bank structure. A micro LED device is within the reflective bank structure and a passivation layer is over the bank layer and laterally around the micro LED device within the reflective bank structure. A portion of the micro LED device and a conductive line atop the bank layer protrude above a top surface of the passivation layer.

A display substrate comprises a base substrate and a first metal layer, a second metal layer, a first electrode pattern, a second electrode pattern, a first insulating layer and a second insulating layer formed above the base substrate. The first insulating layer is located over the first metal layer, the second insulating layer is located above the first insulating layer, the first electrode pattern and the second metal layer are located between the first insulating layer and the second insulating layer; a via hole is arranged at a position directly above the first metal layer to which the first insulating layer and the second insulating layer correspond, one end of the first electrode pattern is connected with the second metal layer, the other end extends into the via hole, the second electrode pattern is in the via hole and connected with the first electrode pattern and the first metal layer.

An array substrate and a display device. The array substrate comprises a common electrode line a plurality of gate lines and a plurality of data lines which intersect with each other and pixel units defined by neighboring in data lines. A storage electrode line is provided, so that storage capacitance between the storage electrode line and the pixel electrode can compensate storage capacitance formed between the common electrode and the pixel electrode. The ability of charge retention of the pixel electrode can be increased, so that voltage of the pixel electrode is constant during display period of a frame, and the display effect of a picture is ensured.