Patent classifications
H10D89/00
SOI SUBSTRATE AND RELATED METHODS
Implementations of a method of making a silicon-on-insulator (SOI) die may include forming a plurality of grooves in a second side of a silicon substrate, depositing an insulative layer directly to the second side of the silicon substrate, the insulative layer filling the plurality of grooves, the silicon substrate comprising a first side opposite the second side, and singulating the silicon substrate through the plurality of grooves into a plurality of SOI die. The insulative layer may be coupled to silicon only through the second side of the silicon substrate.
Semiconductor Die Connection System and Method
A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second semiconductor die with a larger second width and that is still connected to a semiconductor wafer. The first semiconductor die is encapsulated after it is connected, and the encapsulant and first semiconductor die are thinned to expose a through substrate via within the first semiconductor die. The second semiconductor die is singulated from the semiconductor wafer, and the combined first semiconductor die and second semiconductor die are then connected to another substrate.
PIXEL SENSOR WITH MULTI-PROTRUSION TRANSFER GATE
A pixel sensor includes a photodiode including an anode overlying a cathode positioned in a substrate and a transfer transistor structure including a source region extending along a surface of the substrate adjacent to the anode and overlying the cathode, a floating diffusion region extending along the surface of the substrate parallel to the source region, and a gate conductor including an array of conductive protrusions extending into the substrate between the source region and the floating diffusion region.
PIXEL SENSOR WITH MULTI-PROTRUSION TRANSFER GATE
A pixel sensor includes a photodiode including an anode overlying a cathode positioned in a substrate and a transfer transistor structure including a source region extending along a surface of the substrate adjacent to the anode and overlying the cathode, a floating diffusion region extending along the surface of the substrate parallel to the source region, and a gate conductor including an array of conductive protrusions extending into the substrate between the source region and the floating diffusion region.
Electrostatic discharge device with pinch resistor
The present disclosure relates to semiconductor structures and, more particularly, to an electrostatic discharge device (ESD) with a pinch resistor and methods of manufacture. The structure includes: a semiconductor substrate; a shallow trench isolation structure extending into the semiconductor substrate; an amorphous layer in the semiconductor substrate and below the shallow trench isolation structure; and a pinch resistor between the shallow trench isolation structure and the amorphous layer.
EXTRA GATE DEVICE INTEGRATION WITH SEMICONDUCTOR DEVICE
A semiconductor structure includes a first backside source/drain region and a second backside source/drain region in a substrate, associated with an extra gate device, disposed within a backside region of the semiconductor structure.
Forming recesses in molding compound of wafer to reduce stress
A chip includes a semiconductor substrate, an electrical connector over the semiconductor substrate, and a molding compound molding a lower part of the electrical connector therein. A top surface of the molding compound is lower than a top end of the electrical connector. A recess extends from the top surface of the molding compound into the molding compound.
Semiconductor device and semiconductor layout structure
The present disclosure provides a semiconductor device and a semiconductor layout structure. In the semiconductor device, a guard ring of a first type is arranged on at least one side of a transistor of a second type, and a guard ring of a second type is arranged on at least one side of a transistor of a first type, such that a plurality of signal lines in a first metal layer in the semiconductor layout structure may be arranged between a first power source line and a first ground line. Furthermore, in a second metal layer, a plurality of second power source lines are connected to one first power source line, and a plurality of second ground lines are connected to one first ground line.
SHEET FOR WORKPIECE PROCESSING AND MANUFACTURING METHOD OF PROCESSED WORKPIECE
Provided is a sheet for workpiece processing that includes a base material and a pressure sensitive adhesive layer laminated on one side of the base material. The pressure sensitive adhesive layer is composed of an active energy ray-curable pressure sensitive adhesive that contains a hindered amine-based stabilizer. Such a sheet for workpiece processing enables easy separation of workpieces even when a heating treatment is performed.
DICING/DIE-BONDING FILM AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A dicing die-bonding film including a die-bonding film and a dicing film having a pressure-sensitive adhesive layer laminated on the die-bonding film. The thickness of the die-bonding film is 10 m or less. The thickness of the pressure-sensitive adhesive layer is less than 10 m. The dicing film may further have a base material film, and the pressure-sensitive adhesive layer may be provided on the base material film.