A semiconductor device includes: a first conductivity-type collector region; a second conductivity-type field stop region disposed on the collector region; a second conductivity-type drift region, which is disposed on the field stop region and has an impurity concentration lower than the field stop region; a first conductivity-type base region disposed on the drift region; and a second conductivity-type emitter region disposed on the base region, wherein an impurity concentration gradient in a film thickness direction of the field stop region is larger in a region adjacent to the collector region than in a region adjacent to the drift region.

A semiconductor device, including a semiconductor substrate having a diode portion, wherein the diode portion includes: an anode region which is provided on a front surface of the semiconductor substrate and is of a second conductivity type; a trench portion provided so as to extend in a predetermined extending direction on the front surface of the semiconductor substrate; a trench contact portion provided on the front surface of the semiconductor substrate; and a plug region which is provided at a lower end of the trench contact portion and is of a second conductivity type, and which has a doping concentration higher than that of the anode region, wherein a plurality of plug regions, each of which being the plug region, is provided separately from each other along the extending direction, is provided.

In a semiconductor device according to the technology disclosed in the present specification, a temperature detection region is provided with a diffusion layer of a second conductivity type provided on a surface layer of a drift layer of a first conductivity type, a well layer of a first conductivity type provided on a surface layer of the diffusion layer and electrically connected to an anode electrode, and a cathode layer of a first conductivity type provided on a surface layer of the well layer and electrically connected to a cathode electrode.

A semiconductor device with an active transistor cell comprising a p-type first and second base layers, surrounding an n-type source region, the device further comprising a plurality of first gate electrodes embedded in trench recesses, has additional gate runners formed adjacent to the first base layer, outside the active cell, and contacting the first gate electrodes at the cross points thereof. The additional gate runners do not affect the active cell design in terms of cell pitch i.e., the design rules for cell spacing, hole drainage between the cells, or gate-collector capacitance, hence resulting in optimum low conduction and switching losses. The transistor cell and layout designs offer a range of advantages both in terms of performance and manufacturability, with the potential of applying additional layers or structures.

The semiconductor device includes a gate insulation film covering inner surfaces of the first trench and the second trench, and an inner surface of an intersection, and a gate electrode provided in the first trench and the second trench, and facing the semiconductor substrate via the gate insulation film. Further, the semiconductor device includes an emitter region of an n-type provided in the semiconductor substrate, exposed on the front surface of the semiconductor substrate, being in contact with the gate insulation film in the second trench, and not being in contact with the gate insulation film provided on the inner surface of the intersection of the first trench and the second trench.

A voltage-controlled switching device includes a drain/drift structure formed in a semiconductor portion with a lateral cross-sectional area A.sub.Q, a source/emitter terminal, and an emitter channel region between the drain/drift structure and the source/emitter terminal. A resistive path electrically connects the source/emitter terminal and the emitter channel region. The resistive path has an electrical resistance of at least 0.1 m*cm.sup.2/A.sub.Q.

A voltage-controlled switching device includes a drain/drift region of a first conductivity type formed in a semiconductor portion. A channel region and the drain/drift region are in direct contact with each other. A source region of a second conductivity type and the channel region are in direct contact with each other. A gate electrode and the channel region are capacitively coupled and configured such that, in a an on-state of the voltage-controlled switching device, a first enhancement region of charge carriers corresponding to the first conductivity type forms in the channel region and band-to-band tunneling is facilitated between the source region and the first enhancement region.

A voltage-controlled switching device includes a drain/drift region of a first conductivity type formed in a semiconductor portion. A channel region and the drain/drift region are in direct contact with each other. A source region of a second conductivity type and the channel region are in direct contact with each other. A gate electrode and the channel region are capacitively coupled and configured such that, in a an on-state of the voltage-controlled switching device, a first enhancement region of charge carriers corresponding to the first conductivity type forms in the channel region and band-to-band tunneling is facilitated between the source region and the first enhancement region.

Provided is a semiconductor device comprising: a semiconductor substrate provided with a drift region; a buffer region arranged between the drift region and the lower surface, wherein a doping concentration distribution has three or more concentration peaks; and a collector region arranged between the buffer region and the lower surface, wherein the three or more concentration peaks in the buffer region include: a first concentration peak closest to the lower surface; a second concentration peak closest, next to the first concentration peak, to the lower surface, arranged 5 m or more distant from the lower surface in the depth direction, and having a doping concentration lower than the first concentration peak, the doping concentration being less than 1.010.sup.15/cm.sup.3; and a high concentration peak arranged farther from the lower surface than the second concentration peak, and having a higher doping concentration than the second concentration peak.

A field stop insulated gate bipolar transistor (IGBT) fabricated without back-side laser dopant activation or any process temperatures over 450 C. after fabrication of front-side IGBT structures provides activated injection regions with controlled dopant concentrations. Injection regions may be formed on or in a substrate by epitaxial growth or ion implants and diffusion before growth of N field stop and drift layers and front-side fabrication of IGBT active cells. Back-side material removal can expose the injection region(s) for electrical connection to back-side metal. Alternatively, after front-side fabrication of IGBT active cells, back-side material removal can expose the field stop layer (or injection regions) and sputtering using a silicon target with a well-controlled doping concentration can form hole or electron injection regions with well-controlled doping concentration.