When testing a memory chip, the memory chip is determined to be defective if even a portion of the memory chip is defective, and is discarded, which lowers the yield of the three-dimensional memory device. A three-dimensional device is provided comprising a plurality of stacked circuit chips each having one or more circuit blocks in each of a plurality of divided regions obtained by dividing a circuit plane and an interconnect portion communicatively connected, for each group of circuit blocks included in each of the divided regions overlapping in a stacking direction in the plurality of circuit chips, to a predetermined number of circuit blocks sorted from the circuit blocks within the group.

A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.

Provided is a semiconductor device which may include: a channel structure; a gate structure on the channel structure; and a gate contact structure on the gate structure, the gate contact structure configured to receive a gate input signal, wherein the gate contact structure is a portion of the gate structure itself, and no connection surface, interface or boundary is formed between the gate contact structure and the gate structure.

An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

A memory array includes a first bit-line stack disposed over a substrate, a first spacer, a first data storage structure, and a word line. The first bit-line stack includes a first bit line disposed over the substrate; and a first hard mask layer partially covering a top surface of the first bit line. The first spacer is disposed on a lower sidewall of a first sidewall of the first bit line. The first hard mask layer and the first spacer expose a top corner of the first bit line. The first data storage structure covers the top corner of the first bit line. The word line covers a sidewall of the first data storage structure.

A memory array includes a first bit-line stack disposed over a substrate, a first spacer, a first data storage structure, and a word line. The first bit-line stack includes a first bit line disposed over the substrate; and a first hard mask layer partially covering a top surface of the first bit line. The first spacer is disposed on a lower sidewall of a first sidewall of the first bit line. The first hard mask layer and the first spacer expose a top corner of the first bit line. The first data storage structure covers the top corner of the first bit line. The word line covers a sidewall of the first data storage structure.

A super-steep switching device is provided. The super-steep switching device may include a substrate, a semiconductor channel on the substrate, a source electrode and a drain electrode, which are disposed on the semiconductor channel and spaced apart from each other, a gate electrode overlapping a portion of the semiconductor channel and not overlapping a remaining portion of the semiconductor channel, and an insulating layer disposed between the gate electrode and the semiconductor channel and covering an entire surface of the semiconductor channel.

A super-steep switching device is provided. The super-steep switching device may include a substrate, a semiconductor channel on the substrate, a source electrode and a drain electrode, which are disposed on the semiconductor channel and spaced apart from each other, a gate electrode overlapping a portion of the semiconductor channel and not overlapping a remaining portion of the semiconductor channel, and an insulating layer disposed between the gate electrode and the semiconductor channel and covering an entire surface of the semiconductor channel.

A method includes following steps. First transistors are formed over a substrate. An interconnect structure is formed over the plurality of first transistors. A dielectric layer is formed over the interconnect structure. 2D semiconductor seeds are formed over the dielectric layer. The 2D semiconductor seeds are annealed. An epitaxy process is performed to laterally grow a plurality of 2D semiconductor films respectively from the plurality of 2D semiconductor seeds. Second transistors are formed on the plurality of 2D semiconductor films.

Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.