A method of microfabrication includes forming an initial vertical channel structure of semiconductor material protruding from a surface of a substrate such that the initial vertical channel structure has a current flow path that is perpendicular to the surface of the substrate. The initial vertical channel structure is segmented lengthwise into a plurality of independent vertical channel structure segments, each vertical channel structure segment having a respective current flow path that is perpendicular to the surface of the substrate.

A method of microfabrication includes forming an initial vertical channel structure of semiconductor material protruding from a surface of a substrate such that the initial vertical channel structure has a current flow path that is perpendicular to the surface of the substrate. The initial vertical channel structure is segmented lengthwise into a plurality of independent vertical channel structure segments, each vertical channel structure segment having a respective current flow path that is perpendicular to the surface of the substrate.

A semiconductor device includes a first three dimensional (3D) transistor and a second 3D transistor oriented parallel to the first 3D transistor disposed in a substrate, the first 3D transistor and the second 3D transistor being a subset of a plurality of transistors. The device includes a diffusion-break trench disposed in a region laterally separating the second 3D transistor from the first 3D transistor, the diffusion-break trench having a length extending along a lateral direction. The device includes a diffusion-break wire filling the diffusion-break trench, the diffusion-break wire having a height along a vertical direction, gates of the plurality of transistors being made of a different conductive material than the diffusion-break wire.

A semiconductor device includes a first three dimensional (3D) transistor and a second 3D transistor oriented parallel to the first 3D transistor disposed in a substrate, the first 3D transistor and the second 3D transistor being a subset of a plurality of transistors. The device includes a diffusion-break trench disposed in a region laterally separating the second 3D transistor from the first 3D transistor, the diffusion-break trench having a length extending along a lateral direction. The device includes a diffusion-break wire filling the diffusion-break trench, the diffusion-break wire having a height along a vertical direction, gates of the plurality of transistors being made of a different conductive material than the diffusion-break wire.

A device structure according to the present disclosure includes a metal-insulator-metal (MIM) stack that includes a plurality of conductor plate layers interleaved by a plurality of insulator layers. The MIM stack includes a first region and a second region and the first region and the second region overlaps in a third region. The MIM stack further includes a first via passing through the first region and electrically coupled to a first subset of the plurality of conductor plate layers, a second via passing through the second region and electrically coupled to a second subset of the plurality of conductor plate layers, and a ground via passing through the third region and electrically coupled to a third subset of the plurality of conductor plate layers.

A transistor with a high on-state current and a semiconductor device with high productivity are provided. Included are a first oxide, a second oxide, a third oxide, and a fourth oxide over a first insulator; a first conductor over the third oxide; a second conductor over the fourth oxide; a second insulator over the first conductor; a third insulator over the second conductor; a fifth oxide positioned over the second oxide and between the third oxide and the fourth oxide; a sixth oxide over the fifth oxide; a fourth insulator over the sixth oxide; a third conductor over the fourth insulator; and a fifth insulator over the first insulator to the third insulator. The fifth oxide includes a region in contact with the second oxide to the fourth oxide and the first insulator. The sixth oxide includes a region in contact with the fifth oxide, the first conductor, and the second conductor. The fourth insulator includes a region in contact with at least the sixth oxide, the third conductor, and the fifth insulator.

Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.

A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors. For example, a two turn inductor and a three turn inductor may share masks for interconnects and coils, while only masks necessary for connections between the interconnects and coils may need to be newly developed.

A multi-layer semiconductor device includes a first semiconductor structure having first and second opposing surfaces, the second surface of the first semiconductor structure having at least a first semiconductor package pitch. The multi-layer semiconductor device also includes a second semiconductor structure having first and second opposing surfaces, the first surface of the second semiconductor structure having a second semiconductor package pitch. The multi-layer semiconductor device additionally includes a third semiconductor structure having first and second opposing surfaces, the first surface of the third semiconductor structure having a third semiconductor package pitch which is different from at least the second semiconductor package pitch. The second and third semiconductor structures are provided on a same package level of the multi-layer semiconductor device. A corresponding method for fabricating a multi-layer semiconductor device is also provided.

A varainductor includes a spiral inductor, a ground ring, and a floating ring. The floating ring is disposed between the ground ring and the spiral inductor and surrounds a ring portion of the spiral inductor. A switching element, controlled by a switch control signal, selectively electrically connects the ground ring to the floating ring. The switching element includes one or more switches. The one or more switches are controlled by one or more signals of the switch control signal to adjust the inductance level of the varainductor.