Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.

A storage element including a storage layer configured to hold information by use of a magnetization state of a magnetic material, with a pinned magnetization layer being provided on one side of the storage layer, with a tunnel insulation layer, and with the direction of magnetization of the storage layer being changed through injection of spin polarized electrons by passing a current in the lamination direction, so as to record information in the storage layer, wherein a spin barrier layer configured to restrain diffusion of the spin polarized electrons is provided on the side, opposite to the pinned magnetization layer, of the storage layer; and the spin barrier layer includes at least one material selected from the group composing of oxides, nitrides, and fluorides.

Integrated circuits with embedded memory structures, and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes forming first and second conductive interconnects over a semiconductor substrate. The method includes depositing a conductive material over the first conductive interconnect. Also, the method includes forming a memory structure over the conductive material, wherein the memory structure has an uppermost surface distanced from the first conductive interconnect by a first height. Further, the method includes forming an interlayer dielectric over the memory structure and forming a conductive via coupled to the second conductive interconnect, wherein the conductive via has a second height over the second conductive interconnect less than the first height. The method also includes forming first and second contact plugs through the interlayer dielectric. The first contact plug contacts the memory structure and the second contact plug contacts the conductive via.

An integrated circuit die includes a magnetic tunnel junction as a storage element of a MRAM cell. The integrated circuit die includes a top electrode positioned on the magnetic tunnel junction. The integrated circuit die includes a first sidewall spacer laterally surrounding the top electrode. The first sidewall spacer acts as a mask for patterning the magnetic tunnel junction. The integrated circuit die includes a second sidewalls spacer positioned on a lateral surface of the magnetic tunnel junction.

Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.

A method of controlling a trajectory of a perpendicular magnetization switching of a ferromagnetic layer using spin-orbit torques in the absence of any external magnetic field includes: injecting a charge current J.sub.e through a heavy-metal thin film disposed adjacent to a ferromagnetic layer to produce spin torques which drive a magnetization M out of an equilibrium state towards an in-plane of a nanomagnet; turning the charge current J.sub.e off after t.sub.e seconds, where an effective field experienced by the magnetization of the ferromagnetic layer H.sub.eff is significantly dominated by and in-plane anisotropy H.sub.kx, and where M passes a hard axis by precessing around the H.sub.eff; and passing the hard axis, where H.sub.eff is dominated by a perpendicular-to-the-plane anisotropy H.sub.kz, and where M is pulled towards the new equilibrium state by precessing and damping around H.sub.eff, completing a magnetization switching.

A device for guiding charge carriers and uses of the device are proposed, wherein the charge carriers are guided by means of a magnetic field along a curved or angled main path in a two-dimensional electron gas or in a thin superconducting layer, so that a different presence density is produced at electrical connections.

A low temperature deposited (400° C. or less) dielectric passivation layer is formed on physically exposed surfaces of a material stack including a multilayered magnetic tunnel junction (MTJ) pillar and a top electrode. A laser anneal is then performed to improve the physical and chemical properties of the low temperature deposited dielectric passivation layer, without negatively impacting the multilayered MTJ pillar.

The present disclosure provides a skyrmion diode using skyrmions as information carriers. The skyrmion diode includes a magnetic body and a conductive body. The magnetic body has a skyrmion which is used as information carrier. The conductive body is disposed on or under the magnetic body. The conductive body includes a Dzyaloshinskii-Moriya interaction (DMI) region and a defect region. The DMI region is provided to induce DMI in a region of the magnetic body corresponding to the DMI region by the spin-orbit coupling of the conductive body and magnetic moments of the magnetic body. The defect region is provided to prevent the DMI from being induced in a region of the magnetic body corresponding to the defect region.

A base element for switching a magnetization state of a nanomagnet includes a heavy-metal nanostrip having a surface. A ferromagnetic nanomagnet is disposed adjacent to the surface. The ferromagnetic nanomagnet includes a shape having a long axis and a short axis. The ferromagnetic nanomagnet has both a perpendicular-to-the-plane anisotropy H.sub.kz and an in-plane anisotropy H.sub.kx and the ferromagnetic nanomagnet has a first magnetization equilibrium state and a second magnetization equilibrium state. The first magnetization equilibrium state or the second magnetization equilibrium state is settable by a flow of electrical charge through the heavy-metal nanostrip. A direction of flow of the electrical charge through the heavy-metal nanostrip includes an angle ξ with respect to the short axis of the nanomagnet.