Disclosed is a method for the fabrication of a correlated electron material (CEM) switching device, the method comprising: forming a layer of a conductive substrate; forming a layer of a correlated electron material on the conductive substrate; forming a layer of a conductive overlay on the layer of correlated electron material; and patterning the layers whereby to form a stack comprising a conductive substrate, a CEM layer and a conductive overlay, wherein the patterning comprises the following steps: forming a hard mask on the layer of the conductive overlay; dry etching the layer of conductive overlay and the layer of correlated electron material whereby to form a partially formed stack; depositing a coating of a protective polymer over at least sidewalls of the partially formed stack; and dry etching the layer of conductive substrate.

Selector-based electronic devices, inverters, memory devices, and computing devices include a first selector and a second selector. The first selector and the second selector are electrically connected in series between a first voltage source terminal and a second voltage source terminal. The electronic device also includes a transistor electrically connected between an input terminal and a terminal between the first selector and the second selector.

An interconnect structure for on-chip information transfer, and a method for on-chip information transfer. The interconnect structure comprises a source configured for electrically generating plasmons; a detector configured for electrically detecting the generated plasmons; and a plasmonic waveguide coupled between the source and the detector.

Techniques facilitating frequency allocation in multi-qubit circuits are provided. In one example, a computer-implemented method comprises determining, by a device operatively coupled to a processor, an estimated fabrication yield associated with respective qubit chip configurations by conducting simulations of the respective qubit chip configurations at respective frequency offsets; and selecting, by the device, a qubit chip configuration from among the respective qubit chip configurations based on the estimated fabrication yield associated with the respective qubit chip configurations.

A vertical transistor includes two portions of a gate conductor that extend within a layer of insulator. An opening extending through the later of insulator includes source, channel and drain regions form by epitaxy operations. A thickness of the portions of the gate conductor decreases in the vicinity of the channel region.

A surge protection device contains a first electrode, a second electrode electrically connected to electrical ground, and a field-induced switching component electrically contacting the first electrode and the second electrode. The field-induced switching component can include a correlated-electron material or a volatile conductive bridge.

Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, a trench contact formed on and in contact with the source/drain, and a source/drain contact formed on an in contact with the trench contact. A recess is formed in a portion of the source/drain contact using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the source/drain contact. A metallization layer is formed in contact upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.

Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a plurality of source/drains disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, and a plurality of trenches, each trench extending to a corresponding one of the plurality of source/drains. A trench contact is formed in each of the trenches in contact with the corresponding source/drain. A recess is formed in a portion of each trench contact below a top surface of the cap. A bi-stable resistive system (BRS) material is deposited in each recess in contact with the portion of the trench contact. A source/drain contact is formed upon the BRS material, a portion of the trench contact, the BRS material, and a portion of the source/drain contact forming a reversible switch for each of the corresponding source/drains.

A security test logic system can include a non-transitory memory configured to store measurements from a measurement apparatus, the measurement outputs comprising indications of presence or absence of coincidences where particles are detected at more than one detector at substantially the same time, the detectors being at the end of different channels from a particle source and having substantially the same length. The system can include a processor configured to compute a test statistic from the stored measurements. The test statistic may express a Bell inequality, and the system can compare the test statistic with a threshold. The processor can be configured to generate and output a certificate certifying that the measurements are from a quantum system if the value of the computed test statistic passes the threshold.

The present invention provides a method for manufacturing a secondary cell having a plurality of unit cells 21 that are connected in parallel, including, a step to prepare sheet-shaped unit cells each having a structure that a first electrode layer, a metal oxide semiconductor layer, a charging layer, and a second electrode layer are layered, a step to form a cell sheet by connecting the laminated unit cells in parallel, a step to measure a capacity of the cell sheet, and a step to connect a unit cell for capacity adjustment to the cell sheet in parallel when the capacity is smaller than a specification value.