Patent classifications
H01L49/00
Method for manufacturing secondary cell
A method for manufacturing a secondary cell, the secondary cell including a charging layer that captures electrons by forming energy levels in a band gap by causing a photoexcited structural change in an n-type metal oxide semiconductor coated with an insulating material, includes a coating step to coat a coating liquid so as to form a coating film that includes constituents that will form the charging layer; a drying step to dry the coating liquid coated in the coating step; a UV irradiating step to form a UV-irradiated coating film by irradiating the dried coating film obtained through the drying step with ultraviolet light; and a burning step to burn a plurality of the UV-irradiated coating films, after forming the plurality of UV-irradiated coating films by repeating a set plural times, the set including the coating step, the drying step, and the UV irradiating step.
QUANTUM SPIN HALL-BASED CHARGING ENERGY-PROTECTED QUANTUM COMPUTATION
This application concerns quantum computing, and in particular to structures and mechanisms for providing topologically protected quantum computation. In certain embodiments, a magnetic tunnel barrier is controlled that separates Majorona zero modes (MZMs) from an edge area (e.g., a gapless edge) of a quantum spin hall system. In particular implementations, the magnetic tunnel barrier is formed from a pair of magnetic insulators whose magnetization is held constant, and the magnetic tunnel barrier is tuned by controlling a gate controlling the electron density around the magnetic insulator in the QSH plane, thereby forming a quantum dot. And, in some implementations, a state of the quantum dot is read out (e.g., using a charge sensor as disclosed herein).
Quantum Information Processing with Majorana Bound States in Superconducting Circuits
In a weak link of two s-wave superconductors (SCs) coupled via a time-reversal-invariant (TRI) topological superconducting (TSC) island, a Josephson current can flow due to Cooper pairs tunneling in and out of spatially separated Majorana Kramers pairs (MKPs), which are doublets of Majorana bound states (MBSs). The sign of the resulting Josephson current is fixed by the joint parity of the four Majorana bound states that make up the MKPs on the TSC island. This parity-controlled Josephson effect can be used as a read-out mechanism for the joint parity in Majorana-based quantum computing. For a TSC island with four terminals, the SC leads can address a Majorana superconducting qubit (MSQ) formed by the charge ground states of the TSC island's terminals. Cooper pair splitting enables single-qubit operations, qubit read-out, as well as two-qubit entangling gates. Hence, TSC islands between SC leads may provide an alternative approach to superconducting quantum computation.
Wafer-scale integration of vacancy centers for spin qubits
Embodiments of the present disclosure propose two methods for integrating vacancy centers (VCs) on semiconductor substrates for forming VC-based spin qubit devices. The first method is based on using a self-assembly process for integrating VC islands on a semiconductor substrate. The second method is based on using a buffer layer of a III-N semiconductor material over a semiconductor substrate, and then integrating VC islands in an insulating carbon-based material such as diamond that is either grown as a layer on the III-N buffer layer or grown in the openings formed in the III-N buffer layer. Integration of VC islands on semiconductor substrates typically used in semiconductor manufacturing according to any of these methods may provide a substantial improvement with respect to conventional approaches to building VC-based spin qubit devices and may promote wafer-scale integration of VC-based spin qubits for use in quantum computing devices.
Vertical quantum transistor
A vertical transistor includes two portions of a gate conductor that extend within a layer of insulator. An opening extending through the later of insulator includes source, channel and drain regions form by epitaxy operations. A thickness of the portions of the gate conductor decreases in the vicinity of the channel region.
ASYMMETRIC CORRELATED ELECTRON SWITCH OPERATION
Subject matter disclosed herein may relate to correlated electron switches that are capable of asymmetric set or reset operations.
METHOD FOR THE MANUFACTURE OF A CORRELATED ELECTRON MATERIAL DEVICE
Disclosed is a method for the manufacture of a CEM device comprising forming a thin film of a correlated electron material having a predetermined electrical impedance when the CEM device in its relatively conductive (low impedance) state, wherein the forming of the CEM thin film comprises forming a d- or f-block metal or metal compound doped by a physical or chemical vapour deposition with a predetermined amount of a dopant comprising a back-donating ligand for the metal.
Variable resistance device and method for manufacturing same
The forming voltage of a variable resistance device used in a non-volatile memory and the like is decreased, and repetition characteristics are improved. In an element structure in which a metal oxide film is sandwiched between a lower electrode and an upper electrode, an island-shaped/particulate region of amorphous aluminum oxide or aluminum oxycarbide is formed on the metal oxide film. Because an oxide deficiency, serving as the nucleus of a filament for implementing an on/off operation of the variable resistance device, is formed from the beginning under the island-shaped or particulate aluminum oxide or the like, the conventional creation of an oxide deficiency by high-voltage application in the initial period of forming can be eliminated. Such a region can be fabricated using a small number of cycles of an ALD process.
Emitter and method for manufacturing the same
A method for manufacturing an emitter comprises providing a semiconductor substrate having a main surface, the semiconductor substrate comprising a cavity adjacent to the main surface. A portion of the semiconductor substrate arranged between the cavity and the main surface of the semiconductor substrate forms a support structure. The method comprises arranging an emitting element at the support structure, the emitting element being configured to emit a thermal radiation of the emitter, wherein the cavity provides a reduction of a thermal coupling between the emitting element and the semiconductor substrate.
FABRICATION OF CORRELATED ELECTRON MATERIAL DEVICES METHOD TO CONTROL CARBON
Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, precursors, in a gaseous form, may be utilized in a chamber to build a film of correlated electron materials comprising various impedance characteristics.