Techniques facilitating frequency allocation in multi-qubit circuits are provided. In one example, a computer-implemented method comprises determining, by a device operatively coupled to a processor, an estimated fabrication yield associated with respective qubit chip configurations by conducting simulations of the respective qubit chip configurations at respective frequency offsets; and selecting, by the device, a qubit chip configuration from among the respective qubit chip configurations based on the estimated fabrication yield associated with the respective qubit chip configurations.

A security test logic system can include a non-transitory memory configured to store measurements from a measurement apparatus, the measurement outputs comprising indications of presence or absence of coincidences where particles are detected at more than one detector at substantially the same time, the detectors being at the end of different channels from a particle source and having substantially the same length. The system can include a processor configured to compute a test statistic from the stored measurements. The test statistic may express a Bell inequality, and the system can compare the test statistic with a threshold. The processor can be configured to generate and output a certificate certifying that the measurements are from a quantum system if the value of the computed test statistic passes the threshold.

The present invention provides an matter-wave transistor in which the flow of particles (e.g., atoms and molecules) through the transistor is a result of resonant tunneling from a source well, through a gate well and into a drain well (as opposed to being a result of collisions, as in a classical atomtronic transistor). The transistor current of matter-wave particles can be controlled as a function of the breadth of resonant tunneling conditions of the gate well. For example, the resonant tunneling conditions of a gate well that does not include a dipole-oscillating Bose-Einstein condensate (DOBEC) can be broadened by including a DOBEC in the gate well. Similarly, the breadth of resonant tunneling conditions of the gate well can be changed by changing the particle population of a DOBEC in the gate well.

Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) device. In particular embodiments, layers of a CEM to form a correlated electron switch (CES) device may be disposed between layers of electrode material. Use of a metal nitride as an electrode material for at least one terminal of a CES device may simplify processes to implement a CES device in an integrated circuit device such as in back end of line processing.

Described herein are devices incorporating Casimir cavities, which modify the quantum vacuum mode distribution within the cavities. The Casimir cavities can drive charge carriers from or to an electronic device disposed adjacent to or contiguous with the Casimir cavity by modifying the quantum vacuum mode distribution incident on one side of the electronic device to be different from the quantum vacuum mode distribution incident on the other side of the electronic device. The electronic device can exhibit a structure that permits transport or capture of hot carriers in very short time intervals, such as in 1 picosecond or less.

A multiple-atom germanium quantum dot is provided that includes multiple dangling bonds on an otherwise H-terminated germanium surface, each dangling bonds having one of three ionization states of +1, 0 or −1 and corresponding respectively to 0, 1, or 2 electrons in a dangling bond state. The dangling bonds together in close proximity and having the dangling bond states energetically in the germanium band gap with selective control of the ionization state of one of the dangling bonds. A new class of electronics elements is provided through the inclusion of at least one input and at least one output to the multiple dangling bonds. Selective modification or creation of a dangling bond is also detailed.

Some embodiments include a memory cell having a non-ohmic device between a transistor source/drain region and a capacitor. Some embodiments include a memory cell having a transistor with a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. A capacitor is electrically coupled to the second source/drain region through a non-ohmic device. The non-ohmic device includes a non-ohmic-device-material which changes conductivity in response to an electrical property along the channel region. The non-ohmic-device-material has a high-resistivity-mode when the electrical property along the channel region is below a threshold level, and transitions to a low-resistivity-mode when the electrical property along the channel region meets or exceeds the threshold level. Some embodiments include a memory array.

Some embodiments include a memory cell having a non-ohmic device between a transistor source/drain region and a capacitor. Some embodiments include a memory cell having a transistor with a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. A capacitor is electrically coupled to the second source/drain region through a non-ohmic device. The non-ohmic device includes a non-ohmic-device-material which changes conductivity in response to an electrical property along the channel region. The non-ohmic-device-material has a high-resistivity-mode when the electrical property along the channel region is below a threshold level, and transitions to a low-resistivity-mode when the electrical property along the channel region meets or exceeds the threshold level. Some embodiments include a memory array.

An interface for communicating with qubits, the interface including one or more splitters splitting a plurality of signals from a modulated optical carrier and outputting the signals to a plurality of outputs. In one example, the signals include a plurality of different input signals used for exciting or controlling the one or more qubits. In another example, the signals include a plurality of output signals received from the one or more qubits, wherein the output signals used to read one or more states of the one or more qubits.

Some embodiments include a memory cell having a non-ohmic device between a transistor source/drain region and a capacitor. Some embodiments include a memory cell having a transistor with a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. A capacitor is electrically coupled to the second source/drain region through a non-ohmic device. The non-ohmic device includes a non-ohmic-device-material which changes conductivity in response to an electrical property along the channel region. The non-ohmic-device-material has a high-resistivity-mode when the electrical property along the channel region is below a threshold level, and transitions to a low-resistivity-mode when the electrical property along the channel region meets or exceeds the threshold level. Some embodiments include a memory array.