Topological insulators, such as single-crystal Bi.sub.2Se.sub.3 nanowires, can be used as the conduction channel in high-performance transistors, a basic circuit building block. Such transistors exhibit current-voltage characteristics superior to semiconductor nanowire transistors, including sharp turn-on, nearly zero cutoff current, very large On/Off current ratio, and well-saturated output current. The metallic electron transport at the surface with good effective mobility can be effectively separated from the conduction of the bulk topological insulator and adjusted by field effect at a small gate voltage. Topological insulators, such as Bi.sub.2Se.sub.3, also have a magneto-electric effect that causes transistor threshold voltage shifts with external magnetic field. These properties are desirable for numerous microelectronic and nanoelectronic circuitry applications, among other applications.

A system and method of operation embeds a three-dimensional structure in a topology of an analog processor, for example a quantum processor. The analog processor may include a plurality of qubits arranged in tiles or cells. A number of qubits and communicatively coupled as logical qubits, each logical qubit which span across a plurality of tiles or cells of the qubits. Communicatively coupling between qubits of any given logical qubit can be implemented via application or assignment of a first ferromagnetic coupling strength to each of a number of couplers that communicatively couple the respective qubits in the logical qubit. Other ferromagnetic coupling strengths can be applied or assigned to couplers that communicatively couple qubits that are not part of the logical qubit. The first ferromagnetic coupling strength may be substantially higher than the other ferromagnetic coupling strengths.

Disclosed are systems and methods for a quantum-analogue computing bit array consisting of a single qubit analogue, a serial two qubit analogue coupling, or parallel N qubit analogues. The quantum-analogue computing bit array comprises an elastic media having photo-elastic and photo-expansion effects, the adjustment of which allows a manipulation of one or more structural degrees of freedom within the elastic media and one or more temporal degrees of freedom within the elastic media. At least one analogue qubit is defined by one or more elastic waves within the elastic media. The quantum-analogue computing bit array further comprises a modulated light source oriented to illuminate the elastic media with a laser radiation to achieve a non-separable multi-phonon superposition of states within the elastic media.

Provided is a circuit element that includes paired inert electrodes, and a switch layer provided between the paired inert electrodes, that functions as a selection element and a storage element as a single layer, and having a differential negative resistance region in a current-voltage characteristic.

This application concerns quantum computing, and in particular to structures and mechanisms for providing topologically protected quantum computation. In certain embodiments, a magnetic tunnel barrier is controlled that separates Majorona zero modes (“MZMs”) from an edge area (e.g., a gapless edge) of a quantum spin hall system. In particular implementations, the magnetic tunnel barrier is formed from a pair of magnetic insulators whose magnetization is held constant, and the magnetic tunnel barrier is tuned by controlling a gate controlling the electron density around the magnetic insulator in the QSH plane, thereby forming a quantum dot. And, in some implementations, a state of the quantum dot is read out (e.g., using a charge sensor as disclosed herein).

Techniques facilitating frequency allocation in multi-qubit circuits are provided. In one example, a computer-implemented method comprises determining, by a device operatively coupled to a processor, an estimated fabrication yield associated with respective qubit chip configurations by conducting simulations of the respective qubit chip configurations at respective frequency offsets; and selecting, by the device, a qubit chip configuration from among the respective qubit chip configurations based on the estimated fabrication yield associated with the respective qubit chip configurations.

Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, a trench contact formed on and in contact with the source/drain, and a source/drain contact formed on an in contact with the trench contact. A recess is formed in a portion of the source/drain contact using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the source/drain contact. A metallization layer is formed in contact upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.

A first aspect provides a topological quantum computing device comprising a network of semiconductor-superconductor nanowires, each nanowire comprising a length of semiconductor formed over a substrate and a coating of superconductor formed over at least part of the semiconductor; wherein at least some of the nanowires further comprise a coating of ferromagnetic insulator disposed over at least part of the semiconductor. A second aspect provides a method of fabricating a quantum or spintronic device comprising a heterostructure of semiconductor and ferromagnetic insulator, by: forming a portion of the semiconductor over a substrate in a first vacuum chamber, and growing a coating of the ferromagnetic insulator on the semiconductor by epitaxy in a second vacuum chamber connected to the first vacuum chamber by a vacuum tunnel, wherein the semiconductor comprises InAs and the ferromagnetic insulator comprises EuS.

An ion trap chip, which may be used for quantum information processing and the like, includes an integrated microwave antenna. The antenna is formed as a radiator connected by one of its ends to the center trace of a microwave transmission line and connected by its other end to a current return path through a ground trace of the microwave transmission line. The radiator includes several parallel, coplanar radiator traces connected in series. The radiator traces are connected such that they all carry electric current in the same direction, so that collectively, they simulate a single, unidirectionally flowing sheet of current. In embodiments, induced currents in underlying metallization planes are suppressed by parallel slots that extend in a direction perpendicular to the radiator traces.

Subject matter disclosed herein may relate to programmable current for correlated electron switches.