Patent classifications
H10D18/00
4F2 SCR MEMORY DEVICE
A memory-array is disclosed in which an array of threshold switching devices is constructed having an area per transistor of 2F.sup.2. This array of threshold switching devices is suitable for a variety of memory or other applications including PRAM, MRAM, RRAM, FRAM, OPT-RAM and 3-D memory.
RADIO FREQUENCY SWITCHING UNIT, MANUFACTURING METHOD THEREOF AND ELECTRONIC APPARATUS
The present disclosure provides a radio frequency switching unit, a method for manufacturing a radio frequency switching unit and an electronic apparatus, and belongs to the field of radio frequency technology. The radio frequency switching unit of the present disclosure includes: a dielectric substrate, and a first electrode, a second electrode, a metal oxide semiconductor layer, and a barrier layer on the dielectric substrate. The metal oxide semiconductor layer and the barrier layer are both between the first electrode and the second electrode, and the barrier layer is closer to a layer where the first electrode is located than the metal oxide semiconductor layer. The metal oxide semiconductor layer is configured to electrically connect the first electrode to the second electrode through the hollowed-out pattern when an operating voltage is applied between the first electrode and the second electrode.
SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device is provided. The semiconductor device includes: a word line extending in a lateral direction; a sensing line apart from the word line, the sensing line overlapping the word line in a vertical direction and extending in the lateral direction; a vertical semiconductor structure passing through the word line and the sensing line in the vertical direction, the vertical semiconductor structure having a vertical channel region facing the word line in the lateral direction; and a gate dielectric film between the vertical channel region and the word line. The vertical semiconductor structure includes a first heavily doped film of a first conductivity type, a first lightly doped film of a second conductivity type, a second lightly doped film of the first conductivity type, and a second heavily doped film of the second conductivity type, which are sequentially provided in the vertical direction.
Silicon carbide power bipolar devices with deep acceptor doping
In a general aspect, a power semiconductor device can include a collector region disposed on a substrate, the collector region can include n-type silicon carbide (SiC). The power semiconductor device can also include a base region disposed on the collector region. The base region can include p-type SiC doped with gallium. The power semiconductor device can include an emitter region disposed on the base region. The emitter region can include n-type SiC carbide.
Semiconductor device with a semiconductor body containing hydrogen-related donors
A semiconductor device includes a semiconductor body with parallel first and second surfaces and containing hydrogen-related donors. A concentration profile of the hydrogen-related donors vertical to the first surface includes a maximum value of at least 1E15 cm.sup.3 at a first distance to the first surface and does not fall below 1E14 cm.sup.3 over at least 60% of an interval between the first surface and the first distance.
Methods of reading and writing data in a thyristor random access memory
A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array.
METHOD OF FORMING A SEMICONDUCTOR DEVICE TERMINATION AND STRUCTURE THEREFOR
At least one embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several doped layers and a buffer layer.
Semiconductor Devices
A semiconductor device includes a first transistor cell of a plurality of transistor cells of a vertical field effect transistor arrangement, and a second transistor cell of the plurality of transistor cells. The first transistor cell and the second transistor cell are electrically connected in parallel. A gate of the first transistor cell and a gate of the second transistor cell are controllable by different gate control signals.
Method for postdoping a semiconductor wafer
A method for treating a semiconductor wafer having a basic doping is disclosed. The method includes determining a doping concentration of the basic doping, and adapting the basic doping of the semiconductor wafer by postdoping. The postdoping includes at least one of the following methods: a proton implantation and a subsequent thermal process for producing hydrogen induced donors. In this case, at least one of the following parameters is dependent on the determined doping concentration of the basic doping: an implantation dose of the proton implantation, and a temperature of the thermal process.
THYRISTOR RANDOM ACCESS MEMORY DEVICE AND METHOD
Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.