A ferroelectric tunnel junction memory device includes a bit line, a word line and a memory cell located between the bit line and the word line. The memory cell includes a ferroelectric tunneling dielectric portion and an ovonic threshold switch material portion.

A storage apparatus includes a plurality of first wiring layers extending in one direction, a plurality of second wiring layers extending in another direction, and a plurality of memory cells provided in respective opposing regions in which the plurality of first wiring layers and the plurality of second wiring layers are opposed to each other. The plurality of memory cells each includes a selector element layer, a storage element layer, and an intermediate electrode layer provided between the selector element layer and the storage element layer. One or more of the selector element layer, the storage element layer, and the intermediate electrode layer is a common layer that is common between the plurality of memory cells, in which the plurality of memory cells is adjacent to each other and extends in the one direction or the other direction. The intermediate electrode layer includes a nonlinear resistive material.

Described herein are apparatuses, systems, and methods associated with a memory circuit that includes memory cells having respective threshold switches. The memory cells may include a selector transistor with a gate terminal coupled to a word line to receive a word line signal, a drain terminal coupled to a bit line to receive a bit line signal, and a source terminal coupled to a first terminal of the threshold switch. The threshold switch may switch from a high resistance state to a low resistance state when a voltage across the first terminal and a second terminal exceeds a threshold voltage and may remain in the low resistance state after switching when the voltage across the first and second terminals is equal to or greater than a holding voltage that is less than the threshold voltage. Other embodiments may be described and claimed.

A light emitting device including a light emitting element, a light transmissive member, a light guide member, and a light reflective member. The light transmissive member is disposed on an upper surface of the light emitting element, and has a lower surface including a first region facing the light emitting element and a second region positioned outside of the first region. The light guide member covers a lateral surface of the light emitting element and the second region of the lower surface of the light transmissive member. The light reflective member covers the light emitting element, an upper surface of the light transmissive member and the light guide member. One of lateral surfaces of the light transmissive member is exposed from the light reflective member.

An organic light emitting display apparatus includes active patterns arranged corresponding to a plurality of pixels, and connected to each other along a first direction, a first initialization power supply line to which a first initialization voltage is applied, a second initialization power supply line to which a second initialization voltage different from the first initialization voltage is applied, an organic light emitting diode, and an first transistor which apply the second initialization voltage to a first electrode of the organic light emitting diode.

Methods, systems, and devices for access line grain modulation in a memory device are described. A memory cell stack in a cross-point memory array may be formed. In some examples, the memory cell stack may comprise a storage element. A barrier material may be formed above the memory cell stack. The barrier material may initially have an undulating top surface. In some cases, the top surface of the barrier material may be planarized. After the top surface of the barrier material is planarized, a metal layer for an access line may be formed on the top surface of the barrier material. Planarizing the top surface of the barrier material may impact the grain size of the metal layer. In some cases, planarizing the top surface of the barrier material may decrease the resistivity of access lines formed from the metal layer and thus increase current delivery throughout the memory device.

A variable resistance memory device includes a substrate. A first conductive line is disposed on the substrate and extends primarily in a first direction. A second conductive line is disposed on the substrate and extends primarily in a second direction. The second direction intersects the first direction. A phase change pattern is disposed between the first conductive line and the second conductive line. A bottom electrode is disposed between the phase change pattern and the first bottom electrode includes first a first sidewall segment that connects the first conductive line and the phase change pattern to each other. The phase change pattern has a width in the first direction that decreases toward the substrate. The first sidewall segment has a first lateral surface and a second lateral surface that face each other. A lowermost portion of the phase change pattern is disposed between the first lateral surface and the second lateral surface.

Some embodiments relate to an integrated chip including a memory device. The memory device includes a bottom electrode disposed over a semiconductor substrate. An upper electrode is disposed over the bottom electrode. An intercalated metal/dielectric structure is sandwiched between the bottom electrode and the upper electrode. The intercalated metal/dielectric structure comprises a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.

Disclosed is a variable resistance memory device including a first conductive line extending in a first direction parallel to a top surface of the substrate, memory cells spaced apart from each other in the first direction on a side of the first conductive line and connected to the first conductive line, and second conductive lines respectively connected to the memory cells. Each second conductive line is spaced apart in a second direction from the first conductive line. The second direction is parallel to the top surface of the substrate and intersects the first direction. The second conductive lines extend in a third direction perpendicular to the top surface of the substrate and are spaced apart from each other in the first direction. Each memory cell includes a variable resistance element and a select element that are positioned at a same level horizontally arranged in the second direction.

A method includes depositing a bottom electrode layer, a resistance switching element layer, and a top electrode layer over a first dielectric layer; etching the top electrode layer and the resistance switching element layer to form a resistance switching element over the bottom electrode layer and a top electrode over the resistance switching element; depositing a metal-containing compound layer over the top electrode, the resistance switching element, and the bottom electrode layer; and etching the metal-containing compound layer and the bottom electrode layer to form a bottom electrode over the first dielectric layer.