A neuromorphic device includes a synapse. The synapse includes a first electrode, a second electrode spaced apart from the first electrode, an oxygen-containing layer disposed between the first electrode and the second electrode, a reactive metal layer disposed between the oxygen-containing layer and the second electrode, and an oxygen diffusion-retarding layer disposed between the reactive metal layer and the oxygen-containing layer. The oxygen-containing layer includes a P-type material and oxygen ions. The reactive metal layer reacts with the oxygen ions of the oxygen-containing layer. The oxygen diffusion-retarding layer includes an N-type material and interferes with a movement of the oxygen ions from the oxygen-containing layer to the reactive metal layer. An interface between the oxygen-containing layer and the oxygen diffusion-retarding layer is a P-N junction.

A method is presented for forming vertical crossbar resistive random access memory (RRAM) cells. The method includes forming a substantially U-shaped bottom electrode over a substrate, filling the U-shaped bottom electrode with a first conductive material, capping the U-shaped bottom electrode with a dielectric cap, depositing a high-k material, and forming a top electrode such that active areas of the RRAM cells are vertically aligned and the U-shaped bottom electrode is shared between neighboring RRAM cells.

The subject technology is related to methods and apparatus for discretization and manufacturability analysis of computer assisted design models. In one embodiment, the subject technology implements a computer-based method for the reception of an electronic file with a digital model representative of a physical object. The computer-based method determines geometric and physical attributes from a discretized version of the digital model, a cloud point version of the digital model, and symbolic functions generated through evolutionary algorithms. A set of predictive machine learning models is utilized to infer predictions related to the manufacture process of the physical object.

An integrated neuron circuit structure comprising at least one thin-film resistor, one Metal Insulator Metal capacitor and one Negative Differential Resistance device.

Embodiments of the invention are directed to a method and resulting structures for a steep-switch vertical field effect transistor (SS-VFET). In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source or drain region of a substrate. A top source or drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source or drain region. A bi-stable resistive system is formed on the top metallization layer. The bi-stable resistive system includes an insulator-to-metal transition material or a threshold-switching selector. The SS-VFET provides a subthreshold switching slope of less than 60 millivolts per decade.

Switches, breakers that incorporate a phase change material are disclosed, as well as electrical devices including the same. A switch includes a first conductor, a second conductor spaced a distance from the first conductor such that the second conductor does not contact the first conductor, and a switching device electrically coupled to the first conductor, the switching device having a phase change material that, when heated, expands to electrically contact the second conductor.

A phase change memory and a fabrication method are provided. The fabrication method includes: providing a substrate; forming a heating layer on the substrate; forming a phase change layer on and in contact with one sidewall surface of the heating layer. The phase change memory includes: a substrate; a heating layer on the substrate; and a phase change layer on and in contact with one sidewall surface of the heating layer.

Examples herein relate to negative differential resistance devices. An example negative differential resistance device includes a first electrode and a first negative differential resistance device coupled to the first electrode. A second negative differential device is be coupled to the first negative differential resistance device. The second NDR device is different from the first NDR device. A second electrode is coupled to the second NDR device, and is electrically coupled with the first NDR device and the first electrode.

A contact hole structure includes a substrate, an interlayer dielectric (ILD), a conductive layer and an insulating capping layer. The ILD is disposed on the substrate and has a first opening. The conductive layer is disposed in the ILD and aligns the first opening. The insulating capping layer has a spacer disposed on a first sidewall of the first opening, wherein the spacer contacts to the conductive layer and defines a second opening in the first opening, so as to expose a portion of the conductive layer.

Some embodiments relate to a method. A semiconductor substrate is received. The semiconductor substrate has an interconnect structure disposed over a memory region and a logic region of the semiconductor substrate. A bottom electrode and a top electrode are formed over the interconnect structure over the memory region. The bottom electrode is coupled to a lower metal layer in the interconnect structure, and the bottom and top electrode are separated from one another by a data storage or dielectric layer. An interlayer dielectric (ILD) layer is formed over the top electrode. A trench opening having vertical or substantially vertical sidewalls is formed in the ILD layer and exposes an upper surface of the top electrode. An upper metal layer is formed in the trench opening and is in direct contact with the top electrode.