An electronic device comprises a semiconductor memory that includes: a memory cell; a protective layer disposed along a profile of the memory cell; and a buffer layer interposed between at least a portion of a sidewall of the memory cell and the protective layer, wherein the buffer layer and the protective layer include silicon nitride, and wherein a density of the protective layer is greater than a density of the buffer layer.

Embodiments of the present invention include a memory cell that has a vertically-oriented fin. The memory cell may also include a resistive memory device located on a first lateral side of the fin. The resistive memory device may include a bottom electrode, a top electrode, and a resistive element between the bottom electrode and the top electrode. The memory cell may also include a vertical field-effect transistor having a metal gate and a gate dielectric contacting a second lateral side of the fin opposite the first lateral side.

A memory cell includes: a resistive material layer comprising a first portion that extends along a first direction and a second portion that extends along a second direction, wherein the first and second directions are different from each other; a first electrode coupled to a bottom surface of the first portion of the resistive material layer; and a second electrode coupled to the second portion of the resistive material layer.

Provided is an electronic device including a first electrode; a second electrode facing the first electrode; and an active layer between the first electrode and the second electrode, wherein at least one of the first electrode and the second electrode includes a first surface that is closest to the active layer and a second surface that is farthest from the active layer, a size of a cross-sectional horizontal area at the first surface is smaller than a size of a cross-sectional horizontal area at the second surface, the active layer includes a first region, which vertically overlaps the first surface, and a second region outside the first region, and a thickness of the active layer in the first region is smaller than a thickness of the active layer in the second region.

A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.

A new liner structure for improving memory cell design is disclosed that incorporates a boron nitride dielectric layer. An example memory device includes an array of memory cells with each of at least some of the memory cells having a stack of layers, the stack comprising at least one phase change layer. A dielectric layer is provisioned over one or more sidewalls of at least the phase change layer. The dielectric layer comprises both nitrogen and boron. The dielectric layer may be part of a liner structure that includes multiple layers, such as an alternating layer stack of boron nitride and silicon nitride. The dielectric layer can be deposited at low temperature (e.g., less than about 300° C.) while maintaining a low hydrogen content and a relatively high thermal conductivity.

A method for fabricating stacked resistive memory with individual switch control is provided. The method includes forming a first random access memory (ReRAM) device. The method further includes forming a second ReRAM device in a stacked nanosheet configuration on the first ReRAM device. The method also includes forming separate gate contacts for the first ReRAM device and the second ReRAM device.

The present disclosure, in some embodiments, relates to a memory device. The memory device includes a bottom electrode disposed over a lower interconnect within a lower inter-level dielectric (ILD) layer over a substrate. A data storage structure is over the bottom electrode. A first top electrode layer is disposed over the data storage structure, and a second top electrode layer is on the first top electrode layer. The second top electrode layer is less susceptible to oxidation than the first top electrode layer. A top electrode via is over and electrically coupled to the second top electrode layer.

A method for manufacturing a nonvolatile semiconductor storage device includes: forming a first conductive layer by self-alignment on a first wiring layer, and performing an annealing processing; stacking a first stacked film on the first conductive layer; processing the first stacked film, the first conductive layer, and the first wiring layer into a stripe structure extending in a first direction; forming and planarizing a first interlayer insulating film; forming a second wiring layer; forming a second conductive layer by self-alignment on the second wiring layer, and performing an annealing processing; processing the second wiring layer and the second conductive layer into a stripe structure extending in a second direction intersecting the first direction; and processing the first stacked film and the first interlayer insulating film below and between the second wiring layer, and forming a first memory cell having the first stacked film in a columnar shape.

Disclosed is a reconfigurable transistor device having a substrate, a plurality of first transistor fingers disposed in a first region over the substrate, and a phase change switch (PCS) having a patch of a phase change material (PCM) disposed over the substrate in a second region to selectively couple a first set of the plurality of first transistor fingers to a bus, wherein the patch of the PCM is electrically insulating in an amorphous state and electrically conductive in a crystalline state. The PCS further includes a thermal element disposed adjacent to the patch of PCM, wherein the first thermal element is configured to maintain the patch of the PCM to within a first temperature range until the patch of the PCM converts to the amorphous state and maintain the patch of the PCM within a second temperature range until the first patch of PCM converts to the crystalline state.