Disclosed is a method of fabricating a resistive switching memory. A method of fabricating a resistive switching memory according to an embodiment of the present invention includes a step of forming a lower electrode on a substrate; a step of forming a resistive switching layer on the lower electrode using sputtering; and a step of forming an upper electrode on the resistive switching layer, wherein, in the step of forming a resistive switching layer on the lower electrode using sputtering, the substrate is disposed in a region, which is not reached by plasma generated by the first and second targets, between the first target and the second target disposed above the substrate to deposit the resistive switching layer.

A routing structure is disclosed. A first wiring line coupled to a programming access device and a routing block driver and receiver enabling device and a second wiring line coupled to a programming access device and a routing block driver and receiver enabling device. An insulator-metal-transistor device that includes a top electrode, a middle electrode and a bottom electrode, coupled at the intersection of the first wiring line and the second wiring line.

A DIMA semiconductor structure is disclosed. The DIMA semiconductor structure includes a frontend including a semiconductor substrate, a transistor switch of a memory cell coupled to the semiconductor substrate and a computation circuit on the periphery of the frontend coupled to the semiconductor substrate. Additionally, the DIMA includes a backend that includes an RRAM component of the memory cell that is coupled to the transistor switch.

A metasurface unit cell for use in constructing a metasurface array is provided. The unit cell may include a ground plane layer comprising a first conductive material, and a phase change material layer operably coupled to the ground plane layer. The phase change material layer may include a phase change material configured to transition between an amorphous phase and a crystalline phase in response to a stimulus. The unit cell may further include a patterned element disposed adjacent to the phase change material layer and includes a second conductive material. In response to the phase change material transitioning from a first phase to a second phase, the metasurface unit cell may resonate to generate an electromagnetic signal having a defined wavelength. The first phase may be the amorphous phase or the crystalline phase and the second phase may be the other of the amorphous phase or the crystalline phase.

A method of integrating a phase change switch (PCS) into a Bipolar (Bi)/Complementary Metal Oxide Semiconductor (CMOS) (BiCMOS) process, comprises providing a base structure including BiCMOS circuitry on a semiconductor substrate, and forming on the base structure a dielectric contact window layer having metal through-plugs that contact the BiCMOS circuitry. The method includes constructing the PCS on the contact window layer. The PCS includes: a phase change region, between ohmic contacts on the phase change region, to operate as a switch controlled by heat. The method further includes forming, on the contact window layer and the PCS, a stack of alternating patterned metal layers and dielectric layers that interconnect the patterned metal layers, such that the stack connects a first of the ohmic contacts to the BiCMOS circuitry and provides connections to a second of the ohmic contacts and to the resistive heater.

Various embodiments of the present disclosure are directed towards a memory cell comprising a high electron affinity dielectric layer at a bottom electrode. The high electron affinity dielectric layer is one of multiple different dielectric layers vertically stacked between the bottom electrode and a top electrode overlying the bottom electrode. Further, the high electrode electron affinity dielectric layer has a highest electron affinity amongst the multiple different dielectric layers and is closest to the bottom electrode. The different dielectric layers are different in terms of material systems and/or material compositions. It has been appreciated that by arranging the high electron affinity dielectric layer closest to the bottom electrode, the likelihood of the memory cell becoming stuck during cycling is reduced at least when the memory cell is RRAM. Hence, the likelihood of a hard reset/failure bit is reduced.

A memory cell is manufactured by: (a) forming a stack comprising a first layer made of a phase change material and a second layer made of a conductive material; (b) forming a mask on the stack covering only the memory cell location; and (c) etching portions of the stack not covered by the first mask. The formation of the mask covering only the memory cell location comprises defining a first mask extending in a row direction for each row of memory cell locations and then patterning the first mask in a column direction for each column of memory cell locations.

A three-dimensional memory device includes: a plurality of word line groups including a plurality of word lines; a plurality of bit line groups extending in a vertical direction and including a plurality of bit lines spaced apart from the plurality of word lines; a plurality of memory cells arranged between the plurality of word lines and the plurality of bit lines and including a switching component and a variable resistance memory component; a plurality of global bit line groups connected to the plurality of bit line groups, wherein each of the plurality of global bit line groups includes a plurality of global bit lines electrically connected to a plurality of bit lines included in one bit line group, respectively; and a pad structure including a plurality of connection units and a plurality of pad layers, wherein the plurality of connection units are connected to the plurality of word line groups.

Methods, systems, and devices for techniques for memory cells with sidewall and bulk regions in vertical structures are described. A memory cell may include a first electrode, a second electrode, and a self-selecting storage element between the first electrode and the second electrode. The bulk region may extend between the first electrode and the sidewall region. The bulk region may include a chalcogenide material having a first composition, and the sidewall region may include the chalcogenide material having a second composition that is different than the first composition. Also, the sidewall region may separate the bulk region from the second electrode.

Methods, systems, and devices for techniques for memory cells with sidewall and bulk regions in planar structures are described. A memory cell may include a first electrode, a second electrode, and a self-selecting storage element between the first electrode and the second electrode. A conductive path between the first electrode and the second electrode may extend in a direction away from a plane defined by a substrate. The self-selecting storage element may include a bulk region and a sidewall region. The bulk region may include a chalcogenide material having a first composition, and the sidewall region may include the chalcogenide material having a second composition that is different than the first composition. The bulk region and sidewall region may extend between the first electrode and the second electrode and in the direction away from the plane defined by the substrate.