Resistive random access memory (RRAM) cells, for example conductive bridging random access memory (CBRAM) cells and oxygen vacancy-based RRAM (OxRRAM) cells are provided. An RRAM cell may include a metal-insulator-metal (MIM) structure formed between adjacent metal interconnect layers or between a silicided active layer (e.g., including MOSFET devices) and a first metal interconnect layer. The MIM structure of the RRAM cell may be formed by a damascene process including forming a tub opening in a dielectric region, forming a cup-shaped bottom electrode in the tub opening, forming a cup-shaped insulator in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode in an interior opening defined by the cup-shaped insulator. The cup-shaped bottom electrode, or a component thereof (in the case of a multi-layer bottom electrode) may be formed concurrent with interconnect vias, e.g., by deposition of tungsten or other conformal metal.

A semiconductor storage device includes a memory cell including a core portion that extends in a first direction above a semiconductor substrate; a variable resistance layer that extends in the first direction and is in contact with the core portion; a semiconductor layer that extends in the first direction and is in contact with the variable resistance layer; a first insulator layer that extends in the first direction and is in contact with the semiconductor layer; and a first voltage applying electrode that extends in a second direction orthogonal to the first direction and is in contact with the first insulator layer. The core portion is a vacuum region, or a region containing inert gas.

Embodiments of process flows and methods are provided for forming a resistive switching random access memory (ReRAM). More specifically, process flows and methods are provided for reducing the forming voltage needed to form a conductive path in the ReRAM cells. A wide variety of plasma doping processes are used to introduce a plurality of different dopants into a metal-oxide dielectric film. By utilizing at least two different dopants, the plasma doping processes described herein reduce the forming voltage of the subsequently formed ReRAM cell compared to conventional processes that use only one dopant. In some embodiments, the forming voltage may be further reduced by applying a bias power during the plasma doping process, wherein the bias power is preselected to increase the number of ions introduced into the metal-oxide dielectric film during the plasma doping process.

The invention is notably directed to a transflective display device. The device comprises a set of pixels, wherein each of the pixels comprises a portion of bi-stable, phase change material, hereafter a PCM portion, having at least two reversibly switchable states, in which it has two different values of refractive index and/or optical absorption. The device further comprises one or more spacers, optically transmissive, and extending under PCM portions of the set of pixels. One or more reflectors extend under the one or more spacers. An energization structure is in thermal or electrical communication with the PCM portions, via the one or more spacers. Moreover, a display controller is configured to selectively energize, via the energization structure, PCM portions of the pixels, so as to reversibly switch a state of a PCM portion of any of the pixels from one of its reversibly switchable states to the other. A backlight unit is furthermore configured, in the device, to allow illumination of the PCM portions through the one or more spacers. The backlight unit is controlled by a backlight unit controller, which is configured for modulating one or more physical properties of light emitted from the backlight unit. The invention is further directed to related devices and methods of operation.

An electronic switching element is described having, in sequence, a first electrode, a molecular layer bonded to a substrate, and a second electrode. The molecular layer contains compounds of formula I, R.sup.1-(A.sup.1-Z.sup.1).sub.r—B.sup.1—(Z.sup.2-A.sup.2).sub.s-Sp-G, wherein A.sup.1, A.sup.2, B.sup.1, Z.sup.1, Z.sup.2, Sp, G, r, and s are as defined herein, in which a mesogenic radical is bonded to the substrate via a spacer group, Sp, by means of an anchor group, G. The switching element is suitable for production of components that can operate as a memristive device for digital information storage.

An active metamaterial array of the present disclosure includes: a substrate; a plurality of metamaterial structures disposed on the substrate and spaced apart from each other; a conductivity variable material layer formed between each of the plurality of the metamaterial structures so as to selectively connect the metamaterial structures; an electrolyte material layer formed on the metamaterial structures and the conductivity variable material layer; and a gate electrode disposed at one end of the substrate so as to be in contact with one region of the electrolyte material layer, and when an external voltage is applied to the gate electrode, the gate electrode changes the conductivity of the conductivity variable material layer by controlling the migration of ions contained in the electrolyte material layer.

Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, processes are described in which a correlated electron material film may be formed over a conductive substrate by converting at least a portion of the conductive substrate to CEM.

Embedded non-volatile memory structures having selector elements with ballast are described. In an example, a memory device includes a word line. A selector element is above the word line. The selector element includes a selector material layer and a ballast material layer different than the selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the elector element and the bipolar memory element. A bit line is above the word line.

Three-dimensional vertical memory array cell structures and processes. In an exemplary embodiment, a 3D vertical memory array structure is formed by performing operations that include forming an array stack having alternating metal layers and insulator layers, forming a hole through the array stack to expose internal surfaces of the metal layers and internal surfaces of the insulator layers, and performing a metal-oxidation process on the internal surfaces of the metal layers to form selector devices on the internal surfaces of the metal layers. The operations also include depositing one of resistive material or phase-change material within the hole on the selector devices and the internal surfaces of the insulator layers, such that the hole is reduced to a smaller hole, and depositing conductor material in the smaller hole.

A storage device includes a first electrode, a second electrode, and a storage layer. The second electrode is disposed to oppose the first electrode. The storage layer is provided between the first electrode and the second electrode, and includes one or more chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S), transition metal, and oxygen. The storage layer has a non-linear resistance characteristic, and the storage layer is caused to be in a low-resistance state by setting an application voltage to be equal to or higher than a predetermined threshold voltage and is caused to be in a high-resistance state by setting the application voltage to be lower than the predetermined threshold voltage to thereby have a rectification characteristic.