A semiconductor package includes a redistribution structure including redistribution patterns, first and second chip structures on the redistribution structure and electrically connected to the redistribution patterns, a first mold covering at least a portion of each of the first and second chip structures, an interconnection chip including interconnection patterns electrically connected to the redistribution patterns and a plurality of insulating layers having third surfaces in which respective ones of the interconnection patterns are embedded, through-vias electrically connected to the redistribution patterns, a second mold covering at least a portion of each of the through-vias and the interconnection chip. Each third surface includes a first region, and a second region between the first region and an upper surface of the respective interconnection pattern embedded in the third surface. The second region defines a step between the first region and the upper surface of the interconnection pattern embedded in the third surface.

A semiconductor package includes a redistribution structure, a first semiconductor chip above the redistribution structure, a second semiconductor chip on, and offset relative to, the first semiconductor chip, a plurality of first conductive posts extending from a bottom surface of the second semiconductor chip to a top surface of the redistribution structure, a third semiconductor chip on the second semiconductor chip, a plurality of second conductive posts extending from a bottom surface of the third semiconductor chip to the top surface of the redistribution structure, and a molding layer between the top surface of the redistribution structure and the bottom surface of the third semiconductor chip.

Approaches herein relate to methods for forming self-aligned backside contacts and metal sidewall contacts in a semiconductor device. One method may include forming a plurality of alternating first layers and second layers atop a base layer, forming a trench in the plurality of alternating first layers and second layers, and forming a source/drain epitaxial layer along a sidewall of the trench. The method may further include forming a recess in the base layer by extending the trench into the base layer following formation of the source/drain epitaxial layer, filling the recess with a temporary material, and performing an implant by directing ions to the source/drain epitaxial layer after filling the recess with the temporary material, wherein the implant increases an ion concentration along an outer surface of the source/drain epitaxial layer.

A display device according to an embodiment includes a lower substrate, a first bonding electrode disposed on the lower substrate, a first light emitting element disposed on the first bonding electrode, a second bonding electrode disposed on the first light emitting element, and a second light emitting element disposed on the second bonding electrode, the second bonding electrode includes a first distributed Bragg reflector including at least one pair of a first transparent conductive layer and a second transparent conductive layer having different refractive indices that are alternately stacked.

A semiconductor package may include an interposer substrate having first and second surfaces, a through electrode extending through the interposer substrate, an RDL on the first surface of the interposer substrate and an upper surface of the through electrode and including a redistribution wiring structure, first and second semiconductor chips electrically connected to the redistribution wiring structure on the RDL, a first molding member on the RDL and covering sidewalls of the first and second semiconductor chips, a conductive post on the second surface of the interposer substrate and contacting the through electrode, and a second molding member on the second surface of the interposer substrate and covering a sidewall of the conductive post. A maximum width of the through electrode is equal to or greater than that of the conductive post. A length of the through electrode is equal to or less than that of the conductive post.

A semiconductor package may include a first substrate, semiconductor dies stacked on the first substrate in a direction perpendicular to a top surface of the first substrate to have a stepwise structure, a mold layer disposed on the first substrate to cover the semiconductor dies, a second substrate disposed on the mold layer, and vertical conductive lines electrically connecting the semiconductor dies to the second substrate. The first substrate may include a first region and a second region. The first region may have a first thermal expansion coefficient, and the second region may have a second thermal expansion coefficient. The first thermal expansion coefficient may be different from the second thermal expansion coefficient.

A three-dimensional integrated circuit memory device includes a substrate having layers vertically stacked thereon; the layers include: memory cells horizontally arranged to form one row, a word line electrically connected to the plurality of memory cells, and an electrode horizontally extending from the word line and forming a stair structure with other electrodes associated with respective ones of the plurality of layers. Vertically-extending contacts are provided, which electrically contact corresponding electrodes in an open area of each of the layers. A first sub-word line driver has a first driving characteristic and is electrically connected through a first one of the vertically-extending contacts to an electrode associated with a first layer layers. A second sub-word line driver has a second driving characteristic different from the first driving characteristic and is electrically connected through a second one of the vertically-extending contacts to an electrode associated with a second layer among the layers.

A semiconductor package includes: a substrate; four semiconductor chips spaced apart from each other on the substrate, each of the four semiconductor chips including an active surface that is perpendicular to an upper surface of the substrate; wires extending from the active surface of each of the four semiconductor chips, respectively, and electrically connecting the four semiconductor chips and the substrate; and an encapsulant on the substrate and surrounding the four semiconductor chips, wherein upper surfaces and first side surfaces of each of the four semiconductor chips are exposed from the encapsulant.

A display device includes a circuit layer, a display element layer disposed on the circuit layer, and a light control layer disposed on the display element layer. The display element layer may include a first light-emitting element, a second light-emitting element spaced apart from the first light-emitting element in a first direction perpendicular to a thickness direction, a pixel-defining film having first and second pixel openings defined therein, and an organic layer disposed between the circuit layer and the pixel-defining film. The light control layer may include a transmission part having an opening defined therein, and a light blocking part disposed to fill the opening. The first light-emitting element may be disposed on a same layer as the organic layer, and the second light-emitting element may be disposed above the organic layer.

A light emitting element includes a first semiconductor layer doped with an N-type dopant, a second semiconductor layer disposed on the first semiconductor layer and doped with a P-type dopant, an active layer disposed between the first semiconductor layer and the second semiconductor layer, an electrode layer disposed on the second semiconductor layer, and a multilayer insulating film surrounding at least an outer surface of the active layer and including two or more layers, wherein any one insulating film of the multilayer insulating film that is in contact with at least the outer surface of the active layer has a carbon content of about 3% to about 30%.