An integrated chip includes a first metal line disposed over a substrate. A via is disposed directly over a top of the first metal line and the via has a first lower surface and a second lower surface above the first lower surface. A first dielectric structure is disposed laterally adjacent to the first metal line and along a sidewall of the first metal line. A first protective etch-stop structure is disposed directly over a top of the first dielectric structure and vertically separates the second lower surface of the via from the top of the first dielectric structure.

Disclosed herein are methods of forming a microelectronic component. In some embodiments, the methods include providing a substrate having a first surface, forming a first metal feature on the first surface, forming a second metal feature on the first metal feature, forming a dielectric layer over the substrate such that the dielectric layer directly contacts sidewalls of the first and second metal features, and planarizing the dielectric layer to form a second surface for hybrid bonding. After planarizing the dielectric layer, the second metal feature is exposed at the second surface.

A package includes a first die, a second die, an encapsulant, and through insulating vias (TIV). The first die has a first bonding structure. The first bonding structure includes a first dielectric layer and first connectors embedded in the first dielectric layer. The second die has a semiconductor substrate and a second bonding structure over the semiconductor substrate. The second bonding structure includes a second dielectric layer and second connectors embedded in the second dielectric layer. Sidewalls of the second dielectric layer are aligned with sidewalls of the semiconductor substrate. The first connectors are in physical contact with the second connectors. The first connectors and the second connectors are arranged on two opposite sides of an interface between the first dielectric layer and the second dielectric layer. The encapsulant laterally encapsulates the second die. The TIVs are aside the second die.

A semiconductor interconnect structure and formation thereof. The semiconductor interconnect structure includes a subtractively formed via located on top of a lower level metal line. The subtractively formed via has a bottom portion and a top portion. The semiconductor interconnect structure further includes a selectively grown region formed onto the top portion of the subtractively formed via. A portion of the selectively grown region overhangs the bottom portion of the subtractively formed via in one or more directions.

A semiconductor structure is provided. The semiconductor structure includes a lead frame and a sub-substrate disposed on the lead frame, wherein the thickness of the sub-substrate is between 0 and 0.5 m. The semiconductor structure also includes an epitaxial layer disposed on the sub-substrate. The epitaxial layer includes a buffer layer, a channel layer and a barrier layer. The buffer layer is disposed between the sub-substrate and the channel layer. The channel layer is disposed between the buffer layer and the barrier layer. The semiconductor structure further includes a device layer disposed on the barrier layer and an interconnector structure electrically connected to the epitaxial layer and/or the device layer by a through hole.

An embodiment is a method including forming a first interconnect structure over a first substrate, forming a redistribution via over the first interconnect structure, the redistribution via being electrically coupled to at least one of the metallization patterns of the first interconnect structure, forming a redistribution pad over the redistribution via, the redistribution pad being electrically coupled to the redistribution via, forming a first dielectric layer over the redistribution pad, and forming a second dielectric layer over the first dielectric layer. The method also includes patterning the first and second dielectric layers, forming a bond via over the redistribution pad and in the first dielectric layer, the bonding via being electrically coupled to the redistribution pad, the bond via overlapping the redistribution via, and forming a first bond pad over the bonding via and in the second dielectric layer, the first bond pad being electrically coupled to the bond via.

There is provided an image sensor including a semiconductor substrate having a first side and a second side and a photoelectric conversion element disposed at the first side of the semiconductor substrate. In addition, a through electrode is coupled to the photoelectric conversion element, where the through electrode includes a conductive portion and an insulating film. A thickness of the insulating film between the semiconductor substrate and the conductive portion at the first side of the semiconductor substrate is different than the thickness of the insulting film between the semiconductor substrate and the conductive portion at the second side of the semiconductor substrate.

A device includes a substrate, a gate structure, a source/drain region, a first silicide layer, a second silicide layer and a contact. The gate structure wraps around at least one vertical stack of nanostructure channels. The source/drain region abuts the gate structure. The first silicide layer includes a first metal component on the source/drain region. The second silicide layer includes a second metal component different than the first metal component, and is on the first silicide layer. The contact is on the second silicide layer.

The present invention relates to a metal interconnect structure containing no barrier metal and a method of manufacturing the metal interconnect structure. The method includes: filling at least a first interconnect trench with an intermetallic compound by depositing the intermetallic compound on an insulating layer having the first interconnect trench and a second interconnect trench formed in the insulating layer, the second interconnect trench being wider than the first interconnect trench; performing a planarization process of polishing the intermetallic compound until the insulating layer is exposed; and then performing a height adjustment process of polishing the intermetallic compound and the insulating layer until a height of the intermetallic compound in the first interconnect trench reaches a predetermined height.

A semiconductor device includes an insulating layer on a substrate; a via extending from within the substrate and extending through one face of the substrate and a bottom face of a trench defined in the insulating layer such that a portion of a sidewall and a top face of the via are exposed through the substrate; and a pad contacting the exposed portion of the sidewall and the top face of the via. The pad fills the trench. The insulating layer includes a passivation layer on the substrate, and a protective layer is on the passivation layer. An etch stop layer is absent between the passivation layer and the protective layer. A vertical level of a bottom face of the trench is higher than a vertical level of one face of the substrate and is lower than a vertical level of a top face of the passivation layer.