A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A first trench isolation structure is disposed in the substrate between the first device region and the second device region. The first trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is lower than the second bottom surface. The first trench isolation structure includes a first top surface within the first device region and a second top surface within the second device region. The first top surface is coplanar with the second top surface.

A method of making a silicon-on-insulator (SOI) device from a bulk silicon substrate and an SOI device are disclosed. In the method, a stack of a heteroepitaxial layer and a silicon epitaxial layer are formed on a bulk silicon substrate, and a first photolithography process is performed on the stack to form a first trench exposing the bulk silicon substrate. The first trench is filled with a first isolation dielectric, and a second photolithography process is performed on the stack to form a second trench. The first isolation dielectric and the second trench isolate the stack. Subsequently, the heteroepitaxial layer is removed from the stack, forming at least one cavity. Moreover, the at least one cavity is filled with a buried oxide layer. The buried oxide layer and the silicon epitaxial layer overlying the buried oxide layer form SOI substrate structures. SOI devices are formed on the SOI substrate structures.

A method for manufacturing a semiconductor structure includes operations as follows. A substrate is provided, and a mask layer is formed on the substrate. An etching process is performed to form a plurality of first trenches in the mask layer, where the first trench has an inverted trapezoid cross-sectional shape. An epitaxy layer is formed on the substrate, where the epitaxy layer is filled in each of the first trenches to form an active area. The mask layer is removed to form a plurality of second trenches, where the second trench is arranged between adjacent active areas, and the second trench has a regular trapezoid cross-sectional shape. A dielectric layer is filled in the second trench to form an isolation structure.

Disclosed herein are methods for direct bonding. In some embodiments, the direct bonding method includes microwave annealing a dielectric bonding layer of a first element by exposing the dielectric bonding layer to microwave radiation and then directly bonding the dielectric bonding layer of the first element to a second element without an intervening adhesive. The bonding method also includes depositing the dielectric bonding layer on a semiconductor portion of the first element at a first temperature and microwave annealing the dielectric bonding layer at a second temperature lower than the first temperature.

An apparatus configured to reduce lag includes a substrate; a group III-Nitride back barrier layer on the substrate; a group III-Nitride channel layer on the group III-Nitride back barrier layer; a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer include a higher bandgap than a bandgap of the group III-Nitride channel layer; a source electrically coupled to the group III-Nitride barrier layer; a gate on the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; and a p-region being arranged at or below the group III-Nitride barrier layer. Additionally, at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, an area between the gate and the drain.

A silicon carbide semiconductor device has a cell region that includes a main cell region, a sense cell region, and an element isolation region electrically separating the main cell region and the sense cell region. The element isolation region includes a plurality of isolation trenches and a plurality of isolation deep layers of a second conductivity type. The isolation trenches are disposed between the main cell region and the sense cell region, and extend deeper than a base layer to separate the base layer into a section adjacent to the main cell region and a section adjacent to the sense cell region. The isolation deep layers are respectively disposed at bottom portions of the isolation trenches in contact with bottom surfaces of the isolation trenches.

A semiconductor substrate of a reverse conducting IGBT includes a collector layer in contact with a collector electrode, within an IGBT region and a boundary region. The collector layer has a first collector layer provided in the IGBT region and a second collector layer provided in the boundary region. The second collector layer has a lower impurity concentration than the first collector layer.

Disclosed are a Schottky diode and a manufacturing method thereof. The Schottky diode includes a substrate, a first semiconductor layer, a heterostructure layer, a passivation layer, and a cap layer stacked in sequence. The passivation layer includes a first groove and a second groove, and the first groove and the second groove penetrate through at least the passivation layer. A first electrode is arranged at least on the cap layer corresponding to the first groove; a second electrode is arranged in the second groove. A Schottky contact is formed between the first electrode and the cap layers, so that a direct contact area between the first electrode and the heterostructure layer may be avoided, a contradiction between the forward turn-on voltage and the reverse leakage of the Schottky diode may be balanced, and a leakage characteristic of the heterostructure layer in a high temperature environment may be suppressed.

A method of fabricating a semiconductor device includes forming a first shallow trench isolation structure in a first region of a substrate and second shallow trench isolation structures in a second region of the substrate. The method also includes forming a mask layer over the substrate, the first shallow trench isolation structure, and the second shallow trench isolation structures. The method further includes etching the mask layer and second shallow trench isolation structures in the second region sequentially to form a semiconductor protrusion between the second shallow trench isolation structures.

A circuit device includes core circuitry. The circuit device further includes a first plurality of guard rings having a first dopant type, wherein the first plurality of guard rings is around a periphery of the core circuitry. The circuit device further includes a second plurality of guard rings having a second dopant type, wherein the second dopant type is opposite to the first dopant type, and at least one guard ring of the second plurality of guard rings is around a periphery of at least one guard ring of the first plurality of guard rings. Guard rings of the first plurality of guard rings are in a concentric arrangement.