A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.

A package structure and a method for manufacturing a package structure are provided. The package structure includes a substrate, at least one redistribution structure, at least one electronic component and at least one semiconductor die. The substrate has a first surface and a second surface opposite to the first surface. The at least one redistribution structure is disposed on the first surface of the substrate. The at least one electronic component is disposed on the first surface of the substrate. The at least one semiconductor die is disposed on the at least one redistribution structure and electrically connected to the at least one electronic component through the substrate.

A three-dimensional semiconductor memory device may include a substrate, a stack structure including interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate, and vertical channel structures provided in vertical channel holes penetrating the stack structure. Each of the vertical channel structures may include a data storage pattern covering an inner side surface of each of the vertical channel holes, a vertical semiconductor pattern covering the data storage pattern, and a gapfill insulating pattern filling an internal space enclosed by the vertical semiconductor pattern. The vertical semiconductor pattern may have a first surface which is in contact with the gapfill insulating pattern, and a second surface which is in contact with the data storage pattern. A germanium concentration in the vertical semiconductor pattern may decrease in a direction from the first surface toward the second surface.

An integrated circuit device includes a substrate, having a front surface and a rear surface opposite to each other, and a fin-type active region defined by a trench in the front surface, a device separation layer filling the trench, a source/drain region on the fin-type active region, a first conductive plug arranged on the source/drain region and electrically connected to the source/drain region, a power wiring line at least partially arranged on a lower surface of the substrate, a buried rail connected to the power wiring line through the device separation layer and decreasing in horizontal width toward the power wiring line, and a power via connecting the buried rail to the first conductive plug.

An integrated circuit device includes a substrate, having a front surface and a rear surface opposite to each other, and a fin-type active region defined by a trench in the front surface, a device separation layer filling the trench, a source/drain region on the fin-type active region, a first conductive plug arranged on the source/drain region and electrically connected to the source/drain region, a power wiring line at least partially arranged on a lower surface of the substrate, a buried rail connected to the power wiring line through the device separation layer and decreasing in horizontal width toward the power wiring line, and a power via connecting the buried rail to the first conductive plug.

A laminated wiring has a first conductor which connects first terminals of one or more capacitors and each positive terminal of a plurality of semiconductor modules, a second conductor which connects second terminals of the one or more capacitors and each negative terminal of the plurality of semiconductor modules, and an insulator. Slits are cut in at least one of the first conductor and the second conductor (in both of them in the example of FIG. 1). By doing so, among the plurality of semiconductor modules, a variation in the total of respective inductance values between respective first terminals and one positive terminal closest to the respective first terminals and respective inductance values between respective negative terminals to one second terminal closest to the respective negative terminals becomes smaller than or equal to 10 nH.

A laminated wiring has a first conductor which connects first terminals of one or more capacitors and each positive terminal of a plurality of semiconductor modules, a second conductor which connects second terminals of the one or more capacitors and each negative terminal of the plurality of semiconductor modules, and an insulator. Slits are cut in at least one of the first conductor and the second conductor (in both of them in the example of FIG. 1). By doing so, among the plurality of semiconductor modules, a variation in the total of respective inductance values between respective first terminals and one positive terminal closest to the respective first terminals and respective inductance values between respective negative terminals to one second terminal closest to the respective negative terminals becomes smaller than or equal to 10 nH.

In this mounting device (10) for mounting a semiconductor chip (100) on a substrate (104), a controller (50) is provided with: a mounter for pressing the semiconductor chip (100) to the substrate (104) in a state where a cover film (110) is interposed between the semiconductor chip (100) and a thermocompression tool (16), and for heating and then cooling the thermocompression tool (16) to mount the semiconductor chip (100) on the substrate (104); and a separator for heating the thermocompression tool (16) after the semiconductor chip (100) has been mounted, and for raising a mounting head (17) to be separated from the cover film (110).

An electronic device that includes a substrate and a die disposed on the substrate, the die having an active surface. Wire bonds are attached from the active surface of the die to the substrate. A radiation barrier is attached to the substrate and disposed over the die. The radiation barrier is configured to mitigate electromagnetic radiation exposure to the die. A mold compound is formed over the die, the wire bonds, and the radiation barrier.

A semiconductor package device includes a first semiconductor structure, a second semiconductor structure, and a non-metal dopant. The first semiconductor structure includes a first dielectric bonding layer and a first conductive bonding feature disposed in the first dielectric bonding layer. The second semiconductor structure includes a second dielectric bonding layer bonded to the first dielectric bonding layer and a second conductive bonding feature disposed in the second dielectric bonding layer. The first conductive bonding feature is bonded to the second conductive bonding feature to form an interface therebetween. The non-metal dopant is disposed in at least one of the first conductive bonding feature and the second conductive bonding feature.