To provide a thin film capacitor having high adhesion performance with respect to a circuit substrate. A thin film capacitor includes: a metal foil having a roughened upper surface; a dielectric film covering the upper surface of the metal foil and having an opening through which the metal foil is partly exposed; a first electrode layer contacting the metal foil through the opening; and a second electrode layer contacting the dielectric film without contacting the metal foil. The first and second electrode layers are formed in an area surrounded by an outer peripheral area of the upper surface of the metal foil so as not to cover the outer peripheral area. The outer peripheral area of the roughened upper surface of the metal foil is thus exposed, so that adhesion performance with respect to a circuit substrate can be enhanced.

A method for forming a package structure is provided. The method includes transporting a first package component into a processing chamber. The method includes positioning the first package component on a chuck table. The method includes using the chuck table to heat the first package component. The method includes holding a second package component with a bonding head. The bonding head communicates with a plurality of vacuum devices via a plurality of vacuum tubes, and the vacuum devices each operate independently. The method also includes bonding the first package component and the second package component in the processing chamber to form the package structure.

An electronic device includes a semiconductor die having a semiconductor body, a metallization structure over the semiconductor body, a protective overcoat layer over the metallization structure, a polyimide layer over the protective overcoat layer, a crack arrest structure including contiguous metal crack arrest features in the metallization structure that extend from the protective overcoat layer toward the semiconductor body, conductive terminals that extend from the metallization structure through the protective overcoat layer and the polyimide layer, and a protruded metal feature over the crack arrest structure and at least partially abutting the polyimide layer, and a package structure that at least partially encloses the semiconductor die.

A method of fabricating a semiconductor device includes forming a protective structure on at least one die on a substrate. The protective structure exposes one or more electrical contacts on a first surface of the at least one die. Respective terminals are formed on the one or more electrical contacts exposed by the protective structure. Related packages and fabrication methods are also discussed.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a template structure having a first surface and an opposing second surface, wherein the first surface of the template structure is coupled to the surface of the first die, and wherein the template structure includes a cavity at the first surface and a through-template opening extending from a top surface of the cavity to the second surface of the template structure; and a second die within the cavity of the template structure and electrically coupled to the surface of the first die by interconnects having a pitch of less than 10 microns between adjacent interconnects.

A semiconductor structure includes: an interposer including an integrated passive device, a die-side redistribution structure, first on-interposer bump structures, and second on-interposer bump structures. First die-side redistribution wiring interconnects electrically connect electrical nodes within the integrated passive device to the first on-interposer bump structures. Second die-side redistribution wiring interconnects provide a respective electrical connection between a respective pair of second on-interposer bump structures. A first semiconductor die includes first on-die bump structures that are bonded to the first on-interposer bump structures through first solder material portions, and further includes second on-die bump structures that are bonded to the second on-interposer bump structures through second solder material portions. The first semiconductor die includes first metal interconnect structures providing electrical connections between a respective one of the first on-interposer bump structures and a respective one of the second on-interposer bump structures.

Passive devices may be embedded into a cavity in a package substrate, with electrical contacts of the passive device on a contact surface orthogonal to a surface of the package substrate and extending through the package substrate. The electrical contacts of the passive device may be coupled to vias coupled to a power supply to provide capacitive decoupling. One or more through-hole vias (THVs), which provide current to ICs on the package substrate, may be excluded from the package substrate to accommodate the passive device. Embedding the passive devices in the cavity of the package substrate with the contact surface orthogonal to, rather than parallel to, the surface of the package substrate, reduces an area occupied by the passive device. In this manner, a number of the THVs excluded from the package substrate is reduced, which results in a smaller impact to the resistance of the power supply network.

A semiconductor package including a dielectric layer on a substrate and having an opening that partially exposes a top surface of the substrate, a capacitor chip on the substrate and in the opening of the dielectric layer, connection terminals between the substrate and the capacitor chip and connecting the substrate and the capacitor chip to each other, dielectric patches on the substrate and in the opening of the dielectric layer, and an under-fill filling a space between the substrate and the capacitor chip may be provided. The space between the substrate and the capacitor chip includes a first region, a second region, and a third region between the first and second regions. The connection terminals are on the first region and the second region. The dielectric patches are on the third region.

Direct-bonded optoelectronic interconnects for high-density integrated photonics are provided. A combined electrical and optical interconnect enables direct-bonding of fully-processed optoelectronic dies or wafers to wafers with optoelectronic driver circuitry. The photonic devices may be III-V semiconductor devices. Direct-bonding to silicon or silicon-on-insulator (SOI) wafers enables the integration of photonics with high-density CMOS and other microelectronics packages. Each bonding surface has an optical window to be coupled by direct-bonding. Coplanar electrical contacts lie to the outside, or may circumscribe the respective optical windows and are also direct-bonded across the interface using metal-to-metal direct-bonding, without interfering with the optical windows. Direct hybrid bonding can accomplish both optical and electrical bonding in one overall operation, to mass-produce mLED video displays. The adhesive-free dielectric-to-dielectric direct bonding and solder-free metal-to-metal direct bonding creates high-density electrical interconnects on the same bonding interface as the bonded optical interconnect. Known-good-dies may be used, which is not possible conventionally, and photolithography over their top surfaces can scale to high density.

A power semiconductor module includes a flexible first substrate and a flexible second substrate and a first and second power semiconductor switch arranged between the first and second substrate. The first substrate has an electrically conductive first metal layer facing towards the power semiconductor switches, an electrically conductive second metal layer and an electrically non-conductive first insulation film arranged between the first and second metal layer. The second substrate has an electrically non-conductive second insulation film and a third metal layer arranged on the second insulation film. The first and second power semiconductor switch are electrically interconnected by the first and second substrate to form a half-bridge circuit.