A semiconductor die stack includes a first semiconductor die having a first lattice direction, and a second semiconductor die bonded to the first semiconductor die and having a second lattice direction different than the first lattice direction.

A processing method of a bonded wafer includes forming a plurality of modified layers in a form of rings through positioning focal points of laser beams with a wavelength having transmissibility with respect to a first wafer inside the first wafer, from which a chamfered part is to be removed, from a back surface of the first wafer and executing irradiation, holding a second wafer side on a chuck table, and grinding the back surface of the first wafer to thin the first wafer. In the forming the modified layers, the focal points of the laser beams are set in such a manner as to gradually get closer to a joining layer in a direction from an inner side of the first wafer toward an outer side thereof, so that the plurality of ring-shaped modified layers are formed in a form of descending stairs.

A semiconductor device includes a semiconductor substrate, a sealing ring, and at least one routing wiring. The semiconductor substrate has a peripheral region in plan view. The sealing ring is formed on the peripheral region. The sealing ring includes a plurality of conductors and a plurality of first plugs. Each of the plurality of conductors is laminated along a thickness direction of the semiconductor substrate and extends along the peripheral region in plan view. Each of the plurality of conductors has an outer edge and an inner edge in plan view. The plurality of conductors includes a first conductor located at the uppermost layer and a plurality of second conductors located below the first conductor. The outer edge of the first conductor is positioned outside any of outer edges of each of the plurality of second conductors.

A method for forming a semiconductor package structure includes following operations. A first semiconductor wafer is received. The first semiconductor wafer includes a first front side and a first backside. The first semiconductor wafer has a first central region and a first peripheral region. The first semiconductor wafer includes a first interconnect structure in the first central region on the first front side, a first ring structure in the first peripheral region on the first front side, and a first bonding layer over the first ring structure and the first interconnect structure on the first front side. A second semiconductor wafer is received. The second semiconductor wafer has a second front side and a second backside. The second semiconductor wafer includes a second bonding layer disposed on the second front side. The first bonding layer is bonded to the second bonding layer.

A method of manufacturing a laminated wafer with a processed outer circumference includes acquiring a value of joint misalignment between a first wafer and a second wafer of the laminated wafer by measuring the positions of outer circumferences of the first and second wafers, holding the second wafer of the laminated wafer on a holding surface of a holding mechanism, acquiring the position of the first wafer with respect to the holding mechanism while the laminated wafer is being held by the holding mechanism, acquiring the position of the second wafer with respect to the holding mechanism on the basis of the acquired value of joint misalignment and the acquired position of the first wafer, and processing the outer circumference of the first wafer on the basis of the acquired position of the second wafer as a reference.

A method of manufacturing a semiconductor package includes forming a laser groove at a predetermined depth from a front surface of a semiconductor wafer in a cutting area of the semiconductor wafer, performing ashing on the laser groove and removing a heat affected zone, and dividing the semiconductor wafer into individual semiconductor chips by stretching the semiconductor wafer. The laser groove includes two side surfaces angled from the front surface of the semiconductor wafer and opposing each other, and an intersection of the two side surfaces at a lower end of the laser groove forms a tip.

Method of plasma dicing a semiconductor wafer. The method includes a step of providing a semiconductor wafer comprising a main silicon layer and a top silicon oxide layer covered with an organic soft mask. The mask defines a plurality of scribe line regions to be etched. The method includes a step of plasma etching to remove the top silicon oxide layer in the scribe line regions to expose the main silicon layer. The plasma etching is performed using an etch chemistry having gaseous SF.sub.6 gas mixed with gaseous Ar. The method includes a step of plasma etching to remove the main silicon layer in the scribe line regions to provide a plurality of individual semiconductor die.

A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.

A method includes bonding an integrated circuit die to a carrier substrate, forming a gap-filling dielectric around the integrated circuit die and along the edge of the carrier substrate, performing a bevel clean process to remove portions of the gap-filling dielectric from the edge of the carrier substrate, after performing the bevel clean process, depositing a first bonding layer on the gap-filling dielectric and the integrated circuit die, forming a first dielectric layer on an outer sidewall of the first bonding layer, an outer sidewall of the gap-filling dielectric, and the first outer sidewall of the carrier substrate; and bonding a wafer to the first dielectric layer and the first bonding layer, wherein the wafer comprises a semiconductor substrate and a second dielectric layer on an outer sidewall of the semiconductor substrate.

A semiconductor package may include a first semiconductor chip, second semiconductor chips stacked on the first semiconductor chip in a vertical direction, adhesive layers interposed between the first semiconductor chip and one of the second semiconductor chips and between the second semiconductor chips, and a molding member on the first semiconductor chip. Edges of the adhesive layers may be positioned inward from sidewalls of the second semiconductor chips. The molding member may cover at least sidewalls of the second semiconductor chips and sidewalls of the adhesive layers. The molding member may fill edge gaps defined by the sidewalls of the adhesive layers and edges of upper surfaces and lower surfaces of the second semiconductor chips.