METHOD OF PLASMA DICING A SEMICONDUCTOR WAFER

Abstract

Method of plasma dicing a semiconductor wafer. The method includes a step of providing a semiconductor wafer comprising a main silicon layer and a top silicon oxide layer covered with an organic soft mask. The mask defines a plurality of scribe line regions to be etched. The method includes a step of plasma etching to remove the top silicon oxide layer in the scribe line regions to expose the main silicon layer. The plasma etching is performed using an etch chemistry having gaseous SF.sub.6 gas mixed with gaseous Ar. The method includes a step of plasma etching to remove the main silicon layer in the scribe line regions to provide a plurality of individual semiconductor die.

Claims

1. A method of plasma dicing a semiconductor wafer comprising: providing a semiconductor wafer comprising a main silicon layer and a top silicon oxide layer covered with an organic soft mask, the organic soft mask defining a plurality of scribe line regions to be etched; plasma etching to remove the top silicon oxide layer in the plurality of scribe line regions to expose the main silicon layer, wherein the plasma etching is performed using an etch chemistry comprising gaseous SF.sub.6 gas mixed with gaseous Ar; and plasma etching to remove the main silicon layer in the plurality of scribe line regions to provide a plurality of individual semiconductor die.

2. The method according to claim 1, wherein the etch chemistry is an oxygen-free etch chemistry.

3. The method according to claim 1, wherein the etch chemistry is a carbon monoxide-free etch chemistry.

4. The method according to claim 1, wherein the plasma etching to remove the main silicon layer is performed using an etch chemistry comprising gaseous SF.sub.6 gas mixed with gaseous Ar.

5. The method according to claim 1, wherein the organic soft mask comprises a polymer-based mask.

6. The method according to claim 5, wherein the organic soft mask comprises a photoresist mask.

7. The method according to claim 1, wherein the semiconductor wafer is supported on a substrate support.

8. The method according to claim 7, wherein the substrate support is a glass or silicon support structure.

9. The method according to claim 7, wherein the substrate support is a tape and frame assembly.

10. The method according to claim 1, further comprising plasma ashing to remove the organic soft mask.

11. The method according to claim 10, wherein the plasma ashing is performed using an oxygen or argon-based ashing chemistry.

12. The method according to claim 1, wherein the plasma etching to remove the main silicon layer comprises a cyclic Bosch etch process.

13. The method according to claim 1, wherein the semiconductor wafer further comprises one or more metal layers.

14. The method according to claim 1, wherein the plasma etching to remove the top silicon oxide layer is performed at a pressure of 20-50 milli Torr.

15. The method according to claim 1, wherein the plasma etching to remove the top silicon oxide layer is performed using an Ar flow rate of 100-350 sccm.

16. The method according to claim 15, wherein the plasma etching to remove the top silicon oxide layer is performed using an Ar flow rate of 140-170 sccm.

17. The method according to claim 1, wherein the plasma etching to remove the top silicon oxide layer is performed using an SF.sub.6 flow rate of 30-100 sccm.

18. The method according to claim 17, wherein the plasma etching to remove the top silicon oxide layer is performed using an SF.sub.6 flow rate of 40-50 sccm.

19. The method according to claim 1, wherein the etch chemistry to etch the top silicon oxide layer further comprises gaseous C.sub.4F.sub.8.

20. The method according to claim 1, wherein the plasma etching to remove the top silicon oxide layer is at an RF power in a range from 1000-3000 W and an RF bias power in a range from 1500-5000 W.

21. A plasma etch apparatus configured to perform a method according to claim 1, the plasma etch apparatus comprising: a chamber; a plasma generator associated with the chamber and configured to generate a plasma from at least the gaseous SF.sub.6 gas mixed with the gaseous Ar received in the chamber; a substrate support configured to support the semiconductor wafer comprising the main silicon layer and the top SiO.sub.2 layer covered with the organic soft mask, the organic soft mask defining a plurality of scribe line regions to be etched, the substrate support being arranged with respect to the chamber such that in use, the plasma contacts the semiconductor wafer; and a controller configured to cause the plasma etch apparatus to perform a plasma etch to remove the top silicon oxide layer in the plurality of scribe line regions, and subsequently to perform a plasma etch to remove the main silicon layer in the plurality of scribe line regions.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0028] For a fuller understanding of the nature and objects of the disclosure, reference should be made to the following detailed description taken in conjunction with the accompanying figures.

[0029] A prior art method and an embodiment of the present disclosure will now be described by way of example only with reference to the accompanying schematic drawings:

[0030] FIG. 1 illustrates a first step in the prior art method of plasma dicing a semiconductor wafer;

[0031] FIG. 2 illustrates a second step in the prior art method of plasma dicing a semiconductor wafer;

[0032] FIG. 3 illustrates a third step in the prior art method of plasma dicing a semiconductor wafer;

[0033] FIG. 4 illustrates a fourth step in the prior art method of plasma dicing a semiconductor wafer;

[0034] FIG. 5 is a flow diagram of a method of plasma dicing a semiconductor wafer according to the example embodiment of the present disclosure;

[0035] FIG. 6 illustrates a first step in the method of plasma dicing a semiconductor wafer according to the example embodiment of the present disclosure;

[0036] FIG. 7 illustrates a second step in the method of plasma dicing a semiconductor wafer according to the example embodiment of the present disclosure;

[0037] FIG. 8 illustrates a third step in the method of plasma dicing a semiconductor wafer according to the example embodiment of the present disclosure;

[0038] FIG. 9 illustrates a fourth step in the method of plasma dicing a semiconductor wafer according to the example embodiment of the present disclosure; and

[0039] FIG. 10 is a schematic side view of an etch apparatus configured to undertake the method of plasma dicing a semiconductor wafer according to the example embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE DISCLOSURE

[0040] Although claimed subject matter will be described in terms of certain embodiments, other embodiments, including embodiments that do not provide all of the benefits and features set forth herein, are also within the scope of this disclosure. Various structural, logical, process step, and electronic changes may be made without departing from the scope of the disclosure.

[0041] Ranges of values are disclosed herein. The ranges set out a lower limit value and an upper limit value. Unless otherwise stated, the ranges include all values to the magnitude of the smallest value (either lower limit value or upper limit value) and ranges between the values of the stated range.

[0042] The steps of the method described in the various embodiments and examples disclosed herein are sufficient to carry out the methods of the present disclosure. Thus, in an embodiment, the method consists essentially of a combination of the steps of the methods disclosed herein. In another embodiment, the method consists of such steps.

[0043] In a first step of a prior art method of plasma dicing a semiconductor wafer (FIG. 1) there is provided a semiconductor wafer assembly 1 within the chamber of an etch apparatus. The semiconductor wafer assembly 1 comprises a semiconductor wafer 3 supported on a tape 5. The semiconductor wafer 3 comprises a thick silicon substrate layer 7 above the tape 5, and a silicon oxide (SiO.sub.2) layer 9 above the silicon substrate layer 7. The wafer 3 is covered with a polymeric organic mask 11 patterned to define scribe line regions 13 through which the wafer 3 will be plasma etched to separate the wafer into individual dies.

[0044] In a second step of the prior art method (FIG. 2), the silicon oxide layer 9 is plasma etched within the chamber of the etch apparatus using a plasma formed from C.sub.xF.sub.y and/or C.sub.xH.sub.yF.sub.z with O.sub.2 or CO and Ar gases. The etch is directional (anisotropic) so that straight sided walls are formed in the silicon oxide layer 9. Meanwhile, the edges of the mask 11 are etched slightly to provide angled edges. The mask is etched by incoming ions and radicals. However, as not all of the ions are approaching normal to the wafer surface, there is some lateral removal of the mask (most prominently at the top of the mask) resulting in sloped edges. During the etch, inorganic deposits 8 containing fluorine are built up at the edges of the mask 11 and silicon oxide layer 9 in the scribe line regions 13.

[0045] In a third step of the prior art method (FIG. 3), the silicon layer 7 is etched within the chamber of the etch apparatus using a plasma formed from SF.sub.6 or SF.sub.6+Ar gases (with a C.sub.4F.sub.8 deposition step). The etch is undertaken as a rapid anisotropic etch in a cyclic Bosch process (as is known in the art and not described further herein), to form deep channels in the silicon layer 7 having scalloped edges 12.

[0046] In a fourth step of the prior art method (FIG. 4), the polymeric mask 11 is removed by plasma ashing in an oxygen-based strip step. The process of plasma ashing to strip the mask is known in the art and not described further herein. The inorganic deposits 8 remain after the plasma ashing step as unwanted filaments of polymer residue protruding from the sides of the silicon oxide layer at the edges of the separated dies.

[0047] The present disclosure provides a method of plasma dicing a semiconductor wafer which avoids the formation of filaments at the edges of the die.

[0048] In embodiments of the present disclosure, a method of plasma dicing a semiconductor wafer (FIG. 5) comprises at least three steps. The method comprises a first step 101 of providing a semiconductor wafer (for example the wafer shown in FIG. 6 and described in more detail below) comprising a main silicon layer and a top silicon oxide (SiO.sub.2) layer covered with a mask, the mask defining a plurality of scribe line regions to be etched. The method comprises a second step 103 of plasma etching to remove the top silicon oxide layer in the scribe line regions to expose the main silicon layer, wherein the plasma etching is performed using an etch chemistry comprising gaseous SF.sub.6 gas mixed with gaseous Ar. The method comprises a third step 105 of plasma etching to remove the main silicon layer in the scribe line regions to provide a plurality of isolated semiconductor die. By utilizing an etch chemistry comprising gaseous SF.sub.6 gas mixed with gaseous Ar for the silicon oxide etch, the formation of filaments at the edges of the separated dies is avoided during the etch.

[0049] In more detail, in the example embodiment of the present disclosure, in the first step (FIG. 6) there is provided a semiconductor wafer assembly 101 within the chamber of an etch apparatus. The semiconductor wafer assembly 101 comprises a semiconductor wafer 103 supported on a support structure in the example embodiment being a tape 105. The semiconductor wafer 103 comprises a thick silicon substrate layer 107 above the support structure 105, and a silicon oxide (SiO.sub.2) layer 109 above the silicon substrate layer 107. The wafer 103 is covered with a polymeric organic mask 111 patterned to define scribe line regions 113 through which the wafer 103 will be plasma etched. In another embodiment there may be one or more metal layers embedded in the silicon oxide layer 109 for example forming a laminate structure. In the example embodiment of the present disclosure, the semiconductor wafer 103 is a 300 mm wafer. The silicon layer 107 is approximately 40-60 m thick, and the silicon oxide layer 109 is approximately 5-10 m thick. In the example embodiment, the mask 111 is a photoresist mask approximately 3-15 m thick, with 15% open area, defining scribe line regions 113 comprising lanes of width 7-43 m. During curing of the photoresist, the mask deforms slightly, in the example embodiment causing the corners of the mask in the scribe line regions to be angled at an angle of >55%.

[0050] In the example embodiment of the present disclosure, in the second step (FIG. 7), the silicon oxide layer 109 is plasma etched within the chamber of the etch apparatus using a plasma formed from SF.sub.6 and Ar gases. The etch is highly directional (anisotropic) and straight sided walls are formed in the silicon oxide layer 109. In contrast to methods of the prior art, the use of an etch chemistry comprising SF.sub.6 and Ar gases has been found to eliminate the incorporation of inorganic matter such as silicon or fluorine compounds in a polymer layer on the mask and walls of the silicon oxide layer in the vicinity of the etch regions thereby preventing the formation of residual filaments after ashing of the mask. Unwanted contamination of the wafer assembly by fluorine compounds is therefore significantly reduced and/or avoided and corrosion of the die pads and die surfaces is prevented. During the etch the mask may also be somewhat etched, becoming thinner.

[0051] In the example embodiment of the present disclosure, in the third step (FIG. 8), the silicon layer 107 is etched within the chamber of the etch apparatus using a plasma similarly formed from SF.sub.6 and Ar gases. The etch is undertaken as a rapid anisotropic etch in a cyclic Bosch process (as is known in the art and not described further herein), to form deep channels 110 in the silicon having scalloped edges 112. Thus, the wafer 103 is separated into individual dies.

[0052] In the example embodiment of the present disclosure, in a fourth step (FIG. 9), the polymeric mask 111 is removed by plasma ashing in an oxygen-based strip step.

[0053] The plasma ashing to strip the mask is a process known in the art and not described further herein. Due to the use of the etch chemistry comprising Ar and SF.sub.6 for the silicon oxide etch step, there is virtually no polymer residue on the separated dies and consequently no filament formation at the edges of the silicon oxide layer adjacent to the scribe lines. The mask is removed, and no residual filaments are left.

[0054] According to the example embodiment of the present disclosure, all of the steps of the method are undertaken using a plasma etch apparatus (FIG. 10) for example in the first example embodiment of the present disclosure, the Rapier XE TM. In an alternative embodiment, some of the steps, for example the plasma ashing step may be undertaken on a different apparatus.

[0055] The plasma etch apparatus 301 comprises a first chamber 303 disposed above a second larger chamber 305. A first plasma generator 308 in the form of a cylindrical ICP source 309 connected to a first RF (13.56 MHz) power supply 311, is arranged at the periphery of the first chamber, and configured to excite electrons in a gas within the first chamber by generating varying magnetic fields to induce electric fields. A first gas inlet 307 feeds a first process gas (in the example embodiment of the present disclosure being Ar) into the first chamber 303, wherein a primary plasma is generated through electromagnetic induction followed by ion generation.

[0056] A DC coil 313 is used to control the shape of the plasma leaving the first chamber 303. A faraday shield 315 reduces capacitive coupling from the ICP source, i.e. making it predominantly inductive.

[0057] The plasma flows into the second chamber 305 where it contacts the semiconductor wafer assembly 101 supported on an electrostatic chuck 317. The semiconductor wafer assembly 101 (including the tape 105) is held in a frame 323. In the example embodiment, the edge of the semiconductor wafer assembly 101 is protected by a wafer edge protection (WEP) device 319. A baffle 325 above the electrostatic chuck 317 is arranged to control gas flow in the vicinity of the semiconductor wafer assembly.

[0058] A second gas inlet 327 is disposed in an annular arrangement at the top of the second chamber 305 and arranged to feed a second process gas (in the example embodiment of the present disclosure being SF.sub.6) into the second chamber. A second plasma generator 329 connected to a second RF (13.56 MHz) power supply 331 provides a second cylindrical ICP source. A coaxial source helps to increase the etch rate towards the edge of the semiconductor wafer assembly. The second plasma generator 329 is arranged at the periphery of the second chamber and configured to generate a secondary plasma from the second process gas at the periphery of the second chamber 305. The two plasmas mix in the chamber and provide a more evenly distributed plasma over the semiconductor wafer assembly 101.

[0059] The flow of the gas through the chambers is assisted by a pump 335 and valve 333. A separate power supply 337 (also at 13.56 MHz although frequencies of 2-20 MHz could be used) provides an RF bias power on the electrode i.e. support associated with the semiconductor wafer assembly 101.

[0060] In the example embodiment of the present disclosure, the electrostatic chuck 317 is used to control the wafer temperature in the range 15 C. to 10 C. The conditions for the silicon oxide etch were low pressure (in the range 20-50 milli Torr, for example 30 milli Torr), high RF powers (in the range 1000-3000 W, for example 2000 W and 2450 W for the first and second RF power supplies respectively), high RF bias power (in the range 1500-5000 W, for example 2500 W), and moderate gas flow rates (in the range 100-350 sccm for Ar and 30-100 sccm for SF.sub.6, for example 152 sccm and 48 sccm respectively).

[0061] In an alternative embodiment of the present disclosure, a third process gas may be supplied, for example C.sub.4F.sub.8 fed into the second chamber and mixed with the second process gas. In such an embodiment the gaseous C.sub.4F.sub.8 may be fed at a flow rate in the range 5-30 sccm, for example 10 sccm. In such an embodiment the Ar flow rate may be adjusted to 162 sccm, all other etch parameters remaining the same. Addition of C.sub.4F.sub.8 as a third process gas has been found to provide an improved mask/silicon oxide selectivity to 1.2:1 compared to 1:1 which still maintaining a residue-free die outer surface. Accordingly, the SiO.sub.2 etches 1.2 faster than the mask, as opposed to at the same etch rate, which is advantageous as it enables a thinner mask to be used.

[0062] Although the present disclosure has been described with respect to one or more particular embodiments and/or examples, it will be understood that other embodiments and/or examples of the present disclosure may be made without departing from the scope of the present disclosure.