A semiconductor package includes: a substrate; a chip stack on the substrate; a first interface, in a first region of the substrate and having a first circuit layer; a second interface, in a second region of the substrate and having a second circuit layer, and the chip stack between the first and second interface; a first bonding wire, connected to a first chip and having a first contact point; a second bonding wire, connected to a second chip and having a second contact point; an encapsulation layer, surrounding the chip stack, the first and second interface, the first and second bonding wire on the substrate, and exposing the first and second contact point, and the first and second circuit layer; and a redistribution layer, on the encapsulation layer and connecting the first contact point and the second contact point to the first circuit layer and the second circuit layer.

A bonding apparatus includes a chuck table, a gantry frame, a bond head and a gas supplying mechanism. The chuck table is configured to support a semiconductor wafer. The gantry frame is disposed over the chuck table. The bond head is movably installed on the gantry frame, wherein the bond head is configured to pick up a semiconductor chip from a support structure, and for moving the semiconductor chip towards the chuck table for bonding to the semiconductor wafer. The gas supplying mechanism is configured to supply a bonding gas to the semiconductor wafer during the bonding of the semiconductor chip.

Disclosed is a bonded structure including a first microelectronic structure with a first bonding surface and a second microelectronic structure with a second bonding surface directly bonded to the first bonding surface. The first microelectronic structure includes at least one cavity a through the first bonding surface. The second microelectronic structure includes at least one protrusion extending above the second bonding surface. The at least one protrusion of the second microelectronic structure extends within the at least one cavity of the first microelectronic structure without reaching a bottom of the at least one cavity.

Embodiments of the present disclosure provide a semiconductor package. The semiconductor package includes: a first semiconductor chip, a second semiconductor chip, and a first material layer arranged between the first semiconductor chip and the second semiconductor chip, where the first material layer includes a non-conductive substrate as well as a first-type filler and a second-type filler that are distributed in the non-conductive substrate, and the average particle size of the first-type filler is different from the average particle size of the second-type filler. In the embodiments of the present disclosure, two types of fillers with different particle sizes are utilized in combination to increase the filling ratio of the fillers and improve the CTE of the material layers.

A semiconductor package comprises a base chip, a plurality of semiconductor chips sequentially stacked on the base chip, bump structures between the base chip and a lowermost semiconductor chip of the plurality of semiconductor chips, and between the plurality of semiconductor chips, adhesive layers surrounding the bump structures between the base chip and the lowermost semiconductor chip of the plurality of semiconductor chips and between the plurality of semiconductor chips. The adhesive layers have a width equal to or less than a width of each of the plurality of semiconductor chips in a direction parallel to an upper surface of the base chip. At least one of the adhesive layers comprises a polymer resin having a hydrophilic group, a photosensitive compound physically bonded to the polymer resin, and an ionic material crosslinking the polymer resin.

A structure includes a first substrate, a second substrate, and an interface region. The first substrate includes a first layer having at least one electrically conductive first portion and at least one electrically insulative second portion. The second substrate includes a second layer having at least one electrically conductive third portion and at least one electrically insulative fourth portion. The interface region is between the first layer and the second layer and includes at least one electrically conductive polymer material.

An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad.

A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.

Disclosed herein are methods for direct bonding. In some embodiments, a direct bonding method comprises preparing a first bonding surface of a first element for direct bonding to a second bonding surface of a second element; and after the preparing, providing a protective layer over the prepared first bonding surface of the first element, the protective layer having a thickness less than 3 microns.

Disclosed herein are methods for direct bonding. In some embodiments, a direct bonding method comprises preparing a first bonding surface of a first element for direct bonding to a second bonding surface of a second element; and after the preparing, providing a protective layer over the prepared first bonding surface of the first element, the protective layer having a thickness less than 3 microns.