The present application relates to a substrate processing method of suppressing cracking and chipping of a laminated substrate manufactured by bonding substrates, and more particularly to a technique of applying filler to a gap formed between edge portions of the substrates constituting the laminated substrate. The substrate processing method includes: applying a first filler to the gap between an edge portion of a first substrate and an edge portion of a second substrate; and applying a second filler to the gap between the edge portion of the first substrate and the edge portion of the second substrate after applying of the first filler. A viscosity of the first filler is lower than a viscosity of the second filler.

A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a metal-to-metal bond and a heat dissipation feature over the first die. The heat dissipation feature includes a thermal base over the first die and surrounding the second die, wherein the thermal base is made of a metal; and a plurality of thermal vias on the thermal base; and an encapsulant over first die and surrounding the second die, surrounding the thermal base, and surrounding the plurality of thermal vias.

A bonded assembly includes a first semiconductor die containing first semiconductor devices and a first bonding pad embedded within a first silicon oxide layer, where the first bonding pad includes a first copper containing portion, a second semiconductor die containing second semiconductor devices and a second bonding pad that is embedded within a second silicon oxide layer and is bonded to the first bonding pad via metal-to-metal bonding, where the second bonding pad includes a second copper containing portion, and at least one metal silicon oxide layer interposed between the first bonding pad and the second silicon oxide layer. In one embodiment, the at least one metal silicon oxide layer is a manganese silicon oxide layer.

A process flow for bonding a die to a substrate incorporates defectivity risk management and yield promotion by reducing flow complexity. In some embodiments, the process flow may include a radiation process on a component substrate to weaken an adhesive bonding of dies from a surface of the component substrate, a first wet clean process on the component substrate after the radiation process to clean die bonding surfaces, eject and pick processes after performing the first wet clean process to remove dies from the component substrate for bonding to a substrate, a plasma activation process on the substrate, a second wet clean process after the plasma activation process on the substrate to clean a substrate bonding surface of the substrate, and a hybrid bonding process to bond die bonding surfaces of the dies to the substrate bonding surface of the substrate.

A memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, a source layer overlying the first-tier alternating stack, a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the source layer, a memory opening vertically extending through the first-tier alternating stack, the source layer, and the second-tier alternating stack, and a memory opening fill structure located in the memory opening. The memory opening fill structure includes a vertical semiconductor channel that extends through the first-tier alternating stack, the source layer, and the second-tier alternating stack. The vertical semiconductor channel has sidewall in contact with the source layer.

The present invention provides a package structure with an inductor and a manufacturing method thereof, the inductor and the interconnection component are used as n second package module, and stacked with other components such as the first package module to form a stack-like package structure. The first package module is provided with other electronic elements. Then the first and second package modules can be synchronously subjected to package manufacturing, which improves the production efficiency. Additionally, the soldering balls with different heights are formed on the first faces of the interconnecting structural component and the inductive device by adjusting the consumption of soldering paste, which make the second faces of the inductor and the interconnection component are coplanar, then inductor with different heights can form a flat interconnecting plane, which makes the sequential process such as pasting and mounting can be conveniently performed. The process is simplified, and the reliability of the package structure is improved.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a template structure having a first surface and an opposing second surface, wherein the first surface of the template structure is coupled to the surface of the first die, and wherein the template structure includes a cavity at the first surface and a through-template opening extending from a top surface of the cavity to the second surface of the template structure; and a second die within the cavity of the template structure and electrically coupled to the surface of the first die by interconnects having a pitch of less than 10 microns between adjacent interconnects.

An integrated circuit (IC) assembly method is provided. The method includes fabricating a first wafer including a first device with a back end of line (BEOL) and first terminals of first and second types at the BEOL and fabricating a second wafer including a second device for back side power delivery network (BSPDN) processing, second terminals of the first type, first vias and second vias. The first and second wafers are bonded at the BEOL to connect the second terminals of the first type to a subset of the first terminals of the first type, the first vias to remaining first terminals of the first type, and the second vias to the first terminals of the second type. A BSPDN is built onto a backside of the second wafer to include first and second BSPDN terminals connected to the first and second vias, respectively.

A semiconductor memory device includes a substrate, a plurality of first conductive layers arranged in a first direction intersecting with a surface of the substrate, a memory structure including a first semiconductor layer opposed to the first conductive layers, a first wiring, a second conductive layer, a first insulating layer separating the plurality of first conductive layers in a second direction, a second insulating layer separating one or a plurality of the first conductive layers disposed on a side closest to the substrate, and a third insulating layer separating one or a plurality of the first conductive layers disposed on a side farthest from the substrate. The memory structure has a tapered shape having a width in the second direction decreasing with increasing distance from the substrate, and the third insulating layer has a tapered shape having a width in the second direction decreasing with decreasing distance from the substrate.

A semiconductor structure includes: an interposer including an integrated passive device, a die-side redistribution structure, first on-interposer bump structures, and second on-interposer bump structures. First die-side redistribution wiring interconnects electrically connect electrical nodes within the integrated passive device to the first on-interposer bump structures. Second die-side redistribution wiring interconnects provide a respective electrical connection between a respective pair of second on-interposer bump structures. A first semiconductor die includes first on-die bump structures that are bonded to the first on-interposer bump structures through first solder material portions, and further includes second on-die bump structures that are bonded to the second on-interposer bump structures through second solder material portions. The first semiconductor die includes first metal interconnect structures providing electrical connections between a respective one of the first on-interposer bump structures and a respective one of the second on-interposer bump structures.