Methods of making a 3D multilayer semiconductor device, including: providing a first substrate including a first level, the first level including a first single crystal silicon layer (SCSL); providing a second substrate including a second level, the second level including a second SCSL; performing an epitaxial growth of a SiGe layer on top of the second SCSL; performing an epitaxial growth of a third SCSL on top of the SiGe layer, the third SCSL has an average thickness of less than 2,000 nm; forming second transistors each including a single crystal channel, where forming the second transistors includes growth of a second SiGe layer on top of the third SCSL; forming many metal layers interconnecting the second transistors; and then performing a bonding of the second level onto the first level, where performing the bonding includes making oxide-to-oxide bond zones; and performing removal of a majority of the second SCSL.

In an embodiment, a method for producing a substrate having a structured surface includes providing the substrate having a substrate body and having a surface to be structured, forming an absorption layer, a first mask layer and a second mask layer on the surface to be structured, forming openings in the second mask layer in which the first mask layer is exposed, exposing the surface to be structured in a region of the openings, forming depressions in the surface to be structured in the region of the openings to form the structured surface of the substrate and removing the absorption layer from the substrate.

A method of forming a pattern of a semiconductor device includes: preparing a semiconductor substrate including a cell region and an outer region; applying a photoresist on the semiconductor substrate; irradiating extreme ultraviolet (EUV) light reflected from an EUV mask, onto the photoresist; forming a photoresist pattern in the cell region and the outer region; and etching the semiconductor substrate, using the photoresist pattern as an etch mask. The EUV mask includes: a plurality of main patterns in a first zone, of the EUV mask, corresponding to the cell region; and a first lane and a second lane in a second zone, of the EUV mask, corresponding to the outer region, wherein the first lane and the second lane surround the plurality of main patterns, wherein the first lane has a line-and-space pattern, and the second lane has a protruding pattern.

A method of processing a substrate that includes: flowing a fluorocarbon, a metal halide, and dihydrogen (H.sub.2) into a plasma processing chamber, the plasma processing chamber configured to hold a substrate including a dielectric layer including silicon oxide as an etch target and a patterned hardmask including polycrystalline silicon (poly-Si) over the dielectric layer; while flowing the gases, generating a plasma in the plasma processing chamber; and forming a high aspect ratio feature by exposing the substrate to the plasma to etch a recess in the dielectric layer, where a metal-containing passivation layer is formed over the patterned hardmask during the exposing.

The present disclosure discloses a GaN power device having a structure improved to have an improved current density. The GaN power device includes a GaN layer, a first electrode and a second electrode formed on the GaN layer in a way to have a separation area therebetween, an AlGaN layer formed on the GaN layer of the separation area, a gate electrode formed over the AlGaN layer in a way to be separated from the first electrode and the second electrode, and a 2DEG layer formed at an interface of the AlGaN layer and the GaN layer in an area between the gate electrode and the second electrode.

The present disclosure discloses a GaN power device having a structure improved to have an improved current density. The GaN power device includes a GaN layer, a first electrode and a second electrode formed on the GaN layer in a way to have a separation area therebetween, an AlGaN layer formed on the GaN layer of the separation area, a gate electrode formed over the AlGaN layer in a way to be separated from the first electrode and the second electrode, and a 2DEG layer formed at an interface of the AlGaN layer and the GaN layer in an area between the gate electrode and the second electrode.

Methods of forming electronic devices and film stacks comprising depositing a ruthenium carbide hard mask on a capacitor mold formed on a substrate. A hard mask oxide and patterned photoresist are formed, and the pattern of the patterned photoresist are transferred into the ruthenium carbide hard mask. Film stacks comprising the ruthenium carbide hard mask on the capacitor mold are also described.

Provided is a plasma processing method performed with a plasma processing apparatus including a chamber. The method includes: (a) preparing a substrate on a substrate support in the chamber, the substrate including an etching target film and a metal-containing film disposed on the etching target film, the metal-containing film including a side face defining at least one opening on the etching target film; (b) forming a deposited film on at least a portion of the surface of the metal-containing film using a plasma formed from a first processing gas, the first processing gas including a gas containing silicon, carbon or metal; and (c) removing at least a portion of the side face of the metal-containing film using a plasma formed from a second processing gas.

Exemplary semiconductor structures may include a substrate. The structures may include a silicon-and-oxygen material may overlying the substrate. The structures may include a silicon-carbon-and-nitrogen material overlying the silicon-and-oxygen material. The structures may include a metal-doped boron-containing material overlying the silicon-carbon-and-nitrogen material. The metal-doped boron-containing material may be or include a metal dopant comprising tungsten. The structures may include one or more additional materials overlying the metal-doped boron-containing material. The one or more additional materials may be or include a patterned photoresist material.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.