A semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate, and a second dielectric layer disposed over the first dielectric layer. The semiconductor device structure also includes a first semiconductor structure disposed over the second dielectric layer. The first semiconductor structure has a first portion and a second portion separated from each other by an opening. The semiconductor device structure further includes a second semiconductor structure disposed over the second dielectric layer and in the opening. The second semiconductor structure has a first portion and a second portion separated from each other. Moreover, the first portion of the second semiconductor structure is in direct contact with the first portion of the first semiconductor structure, and the second portion of the second semiconductor structure is in direct contact with the second portion of the first semiconductor structure.

An interconnect structure is provided the includes a top electrically conductive via structure that is fully-aligned to a bottom electrically conductive line structure. The interconnect structure has a maximized contact area between the top electrically conductive via structure and the bottom electrically conductive line structure without metal fangs that are caused by over etching. The dielectric surface of the interconnect dielectric material layer that is adjacent to the top electrically conductive via structure is free of reactive ion etch (RIE) damage. Further, there is no line wiggling since the bottom electrically conductive line structure is formed by a substrative metal etch. Further, there is no via distortion since the via opening used to house the top electrically conductive via structure has a density and aspect ratio that are low enough to avoid via distortion.

An etching method includes: providing a substrate having a film and a patterned mask on the film; forming a silicon-containing layer including silicon, carbon, and nitrogen on the substrate using a precursor gas containing silicon; and performing a plasma etching on the film. The substrate is placed under a depressurized environment for a time period from a start time point of the step of forming the silicon-containing layer on the substrate to an end time point of the step of performing the plasma etching on the film.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for optimizing a process of polishing semiconductor wafers. In one aspect, the method comprises repeatedly performing the following: i) selecting a configuration of input settings for polishing a semiconductor wafer, based on a causal model that measures current causal relationships between input settings and a quality of semiconductor wafers; ii) receiving a measure of the quality of the semiconductor wafer polished with the configuration of input settings; and iii) adjusting, based on the measure of the quality of the semiconductor wafer polished with the configuration of input settings, the causal model.

The present invention relates to a substrate processing method, a substrate processing apparatus, and a substrate processing liquid. In the substrate processing method, a substrate W including a first layer G is processed. A second mixed liquid P2 contains an etching liquid and iodide ions (I.sup.). The substrate processing method includes a first adjustment step and an etching step. In the first adjustment step, at least one of oxygen and ozone is added to the second mixed liquid P2. In the etching step, the second mixed liquid P2 adjusted in the first adjustment step is supplied to the substrate W. In the etching step, the first layer G is etched.

A silicon carbide semiconductor device includes a drift layer, a channel layer on the drift layer, the channel layer having a first conductivity type, a trench in the channel layer and a mesa adjacent to the trench, and a gate region within the trench. The gate region has a second conductivity type opposite the first conductivity type, and the gate region includes an epitaxially regrown layer. A method of forming a silicon carbide semiconductor device includes providing a drift layer, forming a channel layer on the drift layer, the channel layer having a first conductivity type, etching the channel layer to form a trench in the channel layer and a mesa adjacent to the trench, and epitaxially regrowing a gate region within the trench, wherein the gate region has a second conductivity type opposite the first conductivity type.

A substrate processing method includes providing a substrate formed with a stacked film including at least an etching target film, an underlying layer disposed below the etching target film, and a mask disposed above the etching target film; etching the etching target film through the mask using plasma; and performing heat treatment on the substrate at a predetermined temperature after the etching. At least one of the mask and the underlying layer contains a transition metal.

A method includes forming first sacrificial layers and first channel layers alternately stacked over a substrate; forming second channel layers and second sacrificial layers alternately stacked over the first sacrificial layers and the first channel layers, in which the second channel layers are made of a first semiconductive oxide; performing an etching process to remove portions of the first sacrificial layers and the second sacrificial layers; forming a gate structure in contact with the first channel layers and the second channel layers; forming first source/drain contacts on opposite sides of the gate structure and electrically connected to the first channel layers; and forming second source/drain contacts on the opposite sides of the gate structure and electrically connected to the second channel layers.

Methods for the fabrication of semiconductor devices are disclosed. A method may include depositing a mask layer on a substrate, forming a protection layer on the mask layer, and modifying the protection layer such that a porosity of the protection layer is reduced. Modifying the protection layer may include densifying the protection layer. Modifying the protection layer may include reducing the protection layer using a hydrogen plasma. The method may include etching the protection layer and the substrate. Etching may include etching, forming the protection layer, and modifying the protection layer in a predetermined number of cycles.

Cerium oxide particles for chemical mechanical polishing and a chemical mechanical polishing slurry composition comprising same are described. A combination of the characteristic cerium oxide particles with a dishing control agent leads to the provision of a chemical mechanical polishing slurry composition that suppresses dishing occurring during the polishing process while enhancing the oxide layer polishing rate, and a method for manufacturing semiconductor devices utilizing same.