Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.

A method includes forming a stack of semiconductor layers over a substrate. The stack includes a first layer including a first semiconductor material over the substrate, a second layer including a second semiconductor material over the first layer, a third layer including the first semiconductor material over the second layer, and a fourth layer including a third semiconductor material over the third layer. The method further includes patterning the stack to form a semiconductor structure, forming a sacrificial gate over the semiconductor structure, forming epitaxial regions adjacent to the sacrificial gate, removing the sacrificial gate to form a recess, selectively removing the first layer and the third layer from the semiconductor structure through the recess to form an opening, selectively removing the second layer from the semiconductor structure through the recess to expand the opening, and forming a replacement gate in the recess and the opening.

A semiconductor device includes a substrate, a gate structure, a drain region and a source region. The substrate includes a first step structure. The first step structure includes a first step portion, a connecting portion and a second step portion arranged sequentially along a direction, and the second step portion is higher than the first step portion. The gate structure is disposed on the connecting portion. The drain region is disposed in the first step portion. The source region is disposed in the second step portion.

A method of forming a via is provided. A lower metal element is formed, and a first patterned photoresist is used to form a sacrificial element over the lower metal element. A dielectric region including a dielectric element projection extending upwardly above the sacrificial element is formed. A second patterned photoresist including a second photoresist opening is formed, wherein the dielectric element projection is at least partially located in the second photoresist opening. A dielectric region trench opening is etched in the dielectric region. The sacrificial element is removed to define a via opening extending downwardly from the dielectric region trench opening. The dielectric region trench opening and the via opening are filled to define (a) an upper metal element in the dielectric region trench opening and (b) a via in the via opening, wherein the via extends downwardly from the upper metal element.

A wafer cleaning apparatus provided by the present invention comprises a rotary shaft, a chuck arranged on the top of the rotary shaft for retaining the wafer, a fixed shaft coaxially passed through the rotary shaft, and an upper end cover and a lower end cover that block the top and bottom of the fixed shaft respectively. Wherein, the fixed shaft is a hollow shaft with at least one circle of exhaust holes provided on the wall of the fixed shaft. The lower end cover is arranged with a gas inlet port, through which a protective gas is provided to the interior of the fixed shaft. The protective gas forms a positive pressure in the annular space between the fixed shaft and the rotary shaft through the at least one circle of exhaust holes. The present invention provides positive pressure protective gas to the spacing between the fixed shaft and the rotary shaft by opening exhaust holes on the wall of the fixed shaft. A gas seal is formed to prevent contaminants, such as particles and metals, generated in the bottom area of the rotary shaft from diffusing to the back side of the wafer through the annular space between the fixed shaft and the rotary shaft, thereby improving the cleanliness of the back side of the wafer after cleaning.

Exemplary semiconductor processing methods may include depositing a metal-doped boron-containing material on a substrate disposed within a processing region of a semiconductor processing chamber. The metal-doped boron-containing material may include a metal dopant comprising tungsten. The substrate may include a silicon-containing material. The methods may include depositing one or more additional materials over the metal-doped boron-containing material. The one or more additional materials may include a patterned photoresist material. The methods may include transferring a pattern from the patterned photoresist material to the metal-doped boron-containing material. The methods may include etching the metal-doped boron-containing material with a chlorine-containing precursor. The methods may include etching the silicon-containing material with a fluorine-containing precursor. The metal dopant may enhance an etch rate of the silicon-containing material. The methods may include removing the metal-doped boron-containing material from the substrate with a halogen-containing precursor.

Embodiments herein are directed to localized wafer thickness correction. In some embodiments, a method may include providing a substrate including an upper surface having a raised portion extending above a plane defined by the upper surface, and a non-raised portion adjacent the raised portion. The method may further include performing a metrology scan of the upper surface to determine a first dimension of the raised portion and a second dimension of the non-raised portion, and depositing a hardmask over the upper surface, including over the raised portion and the non-raised portion. The method may further include directing ions to the hardmask, wherein a first dose of the ions over the raised portion is greater than a second dose of the ions over the non-raised portion, and performing a first etch to the hardmask to remove the hardmask over the raised portion, wherein the hardmask remains over the non-raised portion.

A pressure and force sensor and method of fabrication for the implementation of the sensor is presented that employs piezoresistive elements having high gauge factors. Example embodiments allow for the implementation of a pressure or force sensing device and method of fabrication that can be tailored to the requirements of a wide range of applications without incurring long development times and high costs. The pressure or force sensor has an unprecedented level of sensitivity and can be used to measure extremely low levels of pressure and force, or alternatively to measure extremely high levels of pressure and forces. Moreover, the example embodiments teach pressure and force sensors suitable for use in harsh environments and can be operated at high temperatures.

A method and a tool for film deposition are provided. The method of film deposition includes holding a semiconductor device in a chamber by a holding component, wherein the chamber is defined by a showerhead and a pedestal, providing reacting gases by the showerhead from a bottom side of the chamber, and forming a first dielectric layer on a backside surface of the semiconductor device.

A method for forming a semiconductor device is disclosed herein. The method includes forming a gradient oxide layer on a surface of a substrate, the etch rate of the gradient oxide layer varies along a thickness of the gradient oxide layer, forming a trench through the gradient oxide layer and into the substrate, the trench at least partially defined by a sidewall of the substrate, wherein the surface and the sidewall are connected to form a corner of the substrate, removing a portion of the gradient oxide layer adjacent the corner, wherein a portion of the surface of the substrate is exposed as a result of removing the portion of the gradient oxide layer, and performing an etching process on the exposed corner of the substrate to form a rounded corner that transitions from the surface of the substrate to the sidewall of the substrate.