An etching processing system includes a memory, and a processor coupled to the memory and configured to predict etching quality of a substrate by inputting image data of the substrate into a trained model trained by using training data in which image data of substrates captured by an imaging device arranged on a transfer path of the substrates and information for predicting etching quality of the substrates are associated with each other.

A method includes forming a first masking layer over a substrate, the first masking layer including a first mask line and a second mask line, heating respective top surfaces of the first mask line and the second mask line with polarized light, and forming a second masking layer over the first masking layer with an area selective deposition process. The second masking layer is thinner over a sidewall of the first mask line than over a top surface of the first mask line.

A package structure and a manufacturing method thereof are disclosed. The structure includes at least one semiconductor die, a redistribution layer disposed on the at least one semiconductor die, and connectors there-between. The connectors are disposed between the at least one semiconductor die and the redistribution layer, and electrically connect the at least one semiconductor die and the redistribution layer. The redistribution layer includes a dielectric layer with an opening and a metallic pattern layer disposed on the dielectric layer, and the metallic pattern layer includes a metallic via located inside the opening with a dielectric spacer surrounding the metallic via and located between the metallic via and the opening.

A super junction device may be formed by decreasing the width of the P-type region and increasing the doping concentration, allowing for an increased height of the device. However, instead of etching a trench to fill with the P-type material, a trench may be etched for both the P-type and adjacent N-type regions. This allows the height of the device to be increased while maintaining a feasible aspect ratio for the trench. The P-type material may be formed on the sidewall on the trench to be relatively thin. The trench may then be filled with N-type material such that the P-type region fills the space between the N-type regions without any voids or seams, while having a width that would be unattainable using traditional etch-and-fill methods for the P-type region alone. Wide bandgap materials may also be used to increase the voltage rating.

An etching method includes a preparing step and a removing step. In the preparing step, a substrate is prepared which includes a first film, a second film stacked on the first film, and a hard mask stacked on the second film, such that the second film is etched with the hard mask having a formed pattern as a mask until the first film is exposed. In the removing step, the hard mask is removed using a fluorine-containing gas. Further, the removing step is executed for a time longer than a first time from a start of a supply of the fluorine-containing gas to a start of an etching of the hard mask, and shorter than a second time from the start of the supply of the fluorine-containing gas to a start of an etching of the first film.

A method of preparing a structured substrate of interest including the following steps: providing a substrate of interest including a thin film, onto which a protective layer has been bonded by direct bonding, depositing a resin, and etching the thin film and a portion of the support substrate through openings in the resin, to form pads, bonding a temporary substrate to the substrate of interest, then separating them, whereby the protective layer is separated from the substrate of interest, the resin being removed prior to the bonding step or during the separation, the protective layer/thin film adhesion energy being lower than the temporary substrate/protective layer adhesion energy or than the resin/protective layer adhesion energy.

In an example, a memory device includes a first stack structure and a second stack structure over the first stack structure. Each of the first stack structure and the second stack structure includes alternately stacked conductor layers and first insulating layers. The memory device also includes a first channel structure extending through the first stack structure, and a second channel structure extending through the second stack structure and connected with the first channel structure. A width of an end of the first channel structure closer to the second channel structure is greater than that of the second channel structure closer to the first channel structure. The memory device further includes a pillar structure extending through the first stack structure and the second stack structure. The pillar structure includes a metal layer.

A method of fabricating a semiconductor device comprises forming a mold layer on a substrate, forming a hardmask layer on the mold layer such that a portion of the mold layer is exposed, and using the hardmask layer to perform on the mold layer a cryogenic etching process. The cryogenic etching process includes supplying a chamber with a process gas including first and second process gases, and generating a plasma from the process gas. Radicals of the first process gas etch the exposed portion of the mold layer. Ammonium salt is produced based on the radicals etching the exposed portion of the mold layer. The second process gas includes an ROH compound. The R is hydrogen, a C1 to C5 alkyl group, a C2 to C6 alkenyl group, a C2 to C6 alkynyl group, or a phenyl group. The second process gas reduces a production rate of the ammonium salt.

A method of processing a substrate that includes: forming a bottom passivation layer including an oxide over a first portion of a dielectric layer at a bottom of a recess of the substrate, the recess having sidewalls including a second portion of the dielectric layer; and performing a lateral etch to etch the second portion of the dielectric layer, the bottom passivation layer covering the first portion of the dielectric layer during the lateral etch, and where the forming of the bottom passivation layer includes exposing the substrate to a first plasma including a halogen, and exposing the substrate to a second plasma including oxygen to form the bottom passivation layer.

A method for manufacturing a semiconductor device is disclosed. The method includes forming a mask layer containing a first metal and a first halogen on a film to be processed. The method includes patterning the mask layer. The method includes performing a treatment on the mask layer to decrease the concentration of the first halogen. The method includes processing the film using the treated mask layer as a mask.